Logic gate propagation delay

WHAT is propagation delay?

WHY 50%? Because the "logic threshold" (the voltage the next gate decides is a 1 vs a 0) sits roughly halfway. Measuring at 50% is a consistent, technology-independent reference point.

Note the difference from transition (rise/fall) time: that is measured between the 10% and 90% points of one signal and describes how sharp the edge is — a different quantity.

WHY does delay exist? (Derivation from first principles)

A CMOS gate output drives a load capacitance $C_L$ (wire capacitance + input capacitances of the gates it feeds). When the output switches, a transistor must move charge onto or off that capacitor through its channel resistance $R$ .

Model the switching transistor as a resistor $R$ charging capacitor $C_L$ from supply $V_{DD}$ . By KCL, the current charging the cap equals the current through the resistor:

$C_L\frac{dV}{dt} = \frac{V_{DD}-V}{R}$

Why this step? The same current flows through $R$ and into $C_L$ (series path), and a capacitor's current is $C\,dV/dt$ by definition.

Separate variables and integrate from $V=0$ :

$\frac{dV}{V_{DD}-V} = \frac{dt}{RC_L} \;\Rightarrow\; -\ln(V_{DD}-V) = \frac{t}{RC_L} + k$

Applying $V(0)=0$ gives $k=-\ln V_{DD}$ , so:

$\boxed{V(t) = V_{DD}\left(1 - e^{-t/RC_L}\right)}$

Why this step? This is the standard exponential charging curve — the output does not jump; it eases up to $V_{DD}$ with time constant $\tau = RC_L$ .

Now find $t_{pLH}$ : the time to reach the 50% point $V = V_{DD}/2$ :

$\frac{V_{DD}}{2} = V_{DD}(1-e^{-t/RC_L}) \;\Rightarrow\; e^{-t/RC_L} = \tfrac12 \;\Rightarrow\; t = RC_L\ln 2$

Consequences you can now predict (Forecast-then-Verify):

Drive more gates → larger $C_L$ → more delay. (Fan-out costs time.)
Use a bigger/stronger transistor → smaller $R$ → less delay (but bigger input cap for the previous gate!).
Longer wires → more $C_L$ → more delay.

Delays ADD along a path

Worked examples

Common mistakes

Active recall

Recall Try before revealing

Define $t_{pd}$ and the reference points used.
Derive $t_{pd}=0.69RC_L$ from the RC charging equation.
Why does fan-out increase delay?
What causes a static hazard glitch?

What is propagation delay of a logic gate?

The time from the input crossing 50% of its voltage swing to the output crossing 50%, in response to that change.

Why is delay measured at the 50% point?

Because the logic threshold (where the next gate decides 0 vs 1) is ~halfway, giving a consistent technology-independent reference.

What are t_pLH and t_pHL?

Delays for the output going Low→High and High→Low respectively.

Derive the delay formula: what equation governs the output rising?

C_L dV/dt = (V_DD − V)/R, giving V(t)=V_DD(1−e^(−t/RC_L)).

What is the propagation delay in terms of R and C_L?

t_pd ≈ 0.69·R·C_L (since ln2 ≈ 0.693).

Why does delay increase with fan-out?

More gates driven = larger load capacitance C_L, and delay ∝ C_L.

How do delays combine through a chain of gates?

They ADD along a path; the longest (critical) path sets the max clock frequency f_max = 1/t_critical.

Difference between propagation delay and rise time?

Propagation delay is 50%(in)→50%(out) between two signals; rise/fall time is 10%→90% of ONE signal (edge sharpness).

What is a static hazard (glitch)?

A brief false output pulse caused by unequal path delays making inputs to a gate arrive at different times.

Does making the driving transistor bigger always speed the circuit?

No — smaller R helps, but its larger input capacitance slows the previous stage; it's a trade-off.

Recall Feynman: explain to a 12-year-old

Imagine filling a cup with water through a thin straw. Even if you decide instantly to fill it, the water still takes a moment to rise to the halfway line. A logic gate is like that: the "water" is electric charge, the "cup" is a tiny capacitor, and the "straw" is the transistor's resistance. The gate knows the answer immediately, but it takes a little time to actually push the voltage up to where the next gate can read it. Chain many cups and straws together, and the waiting times add up — that's why fast computers work hard to keep those straws fat and the cups small.

Connections

Boolean Algebra & Logic Gates — logic layer that this timing layer sits on top of
CMOS transistor structure — the $R$ and $C_L$ come from real MOSFETs
RC circuits and time constant — source of the $0.69RC$ result
Static and dynamic hazards — glitches caused by delay mismatch
Critical path and clock frequency — how $t_{pd}$ limits $f_{max}$
Fan-out and loading — why driving many gates is slow

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, logic gate ka truth table batata hai output kya hoga, lekin ye kabhi nahi batata ki output kab milega. Real hardware me har gate transistors se bana hota hai, aur transistor ke through ek chhoti capacitor charge karni padti hai. Capacitor ko charge hone me time lagta hai — bilkul jaise patli straw se glass bharne me time lagta hai. Isi waiting time ko hum propagation delay ( $t_{pd}$ ) kehte hain, aur ye input ke 50% se output ke 50% tak measure hota hai.

Formula derive karna simple hai: current $R$ aur $C_L$ dono me se same behta hai, to $C_L\,dV/dt=(V_{DD}-V)/R$ . Isko solve karo to output exponential tarah upar chadhta hai: $V(t)=V_{DD}(1-e^{-t/RC_L})$ . Jab output 50% pe pahunchta hai tab $t=RC_L\ln2$ , yaani $t_{pd}\approx 0.69\,RC_L$ . Matlab jitni zyada load capacitance (zyada gates drive karo, lambe wires), utni zyada delay. Ye baat yaad rakho — fan-out free nahi hota, time lagta hai.

Aur ek important cheez: agar gates chain me lage hain, to delays add hoti hain, average nahi. Sabse lamba path (critical path) hi decide karta hai ki chip kitni fast clock chala sakti hai: $f_{max}=1/t_{critical}$ . Jab do inputs alag-alag time pe pahunchte hain (unequal delay), to ek chhota galat pulse aa sakta hai jise glitch ya static hazard kehte hain. Isliye engineers transistor sizing aur wiring bahut dhyan se karte hain — logic sahi ho ye kaafi nahi, timing bhi sahi honi chahiye.

WHAT is propagation delay?

WHY does delay exist? (Derivation from first principles)

Delays ADD along a path

Worked examples

Common mistakes

Active recall

Connections

Concept Map

Hinglish (regional understanding)

Go deeper — visual, from zero

Test yourself — Boolean Algebra & Logic Gates

Connections