3.2.13CMOS Circuit Design

Power-delay product

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WHAT is the Power-Delay Product?

WHY does multiplying power by delay give energy? Power is energy-per-second (P=E/tP=E/t). If a gate takes tpt_p seconds to switch, then the energy for that one switch is E=P×tpE = P\times t_p. So PDP is not an arbitrary "figure of merit" — it is a real physical quantity: the energy the circuit pays each time it flips.


HOW we derive PDP from first principles (CMOS)

We derive the dynamic energy of a CMOS gate charging a load capacitor CLC_L.

Step 1 — Charge the capacitor from 0 to VDDV_{DD}. Why this step? A CMOS output rising to logic-1 means the PMOS network pulls CLC_L up to VDDV_{DD}. The energy drawn from the supply is what we must account for.

Charge delivered: Q=CLVDDQ = C_L V_{DD}. Energy drawn from supply during a full charge: Esupply=0VDDi(t)dt=VDD0idt=VDDQ=CLVDD2E_{supply} = \int_0^\infty V_{DD}\, i(t)\,dt = V_{DD}\int_0^\infty i\,dt = V_{DD}\,Q = C_L V_{DD}^2

Step 2 — Where does that energy go? Why this step? Energy must be conserved; half is stored, half is burned.

Energy stored on the capacitor: Ecap=12CLVDD2E_{cap}=\tfrac12 C_L V_{DD}^2. Energy dissipated in the PMOS resistance while charging: EsupplyEcap=12CLVDD2E_{supply}-E_{cap}=\tfrac12 C_L V_{DD}^2.

Step 3 — Discharge (output falls to 0). Why this step? When output goes 1→0, the stored 12CLVDD2\tfrac12 C_L V_{DD}^2 is dumped through the NMOS and burned as heat.

Step 4 — Energy per full cycle (one up + one down): Ecycle=12CLVDD2+12CLVDD2=CLVDD2E_{cycle}= \tfrac12 C_L V_{DD}^2 + \tfrac12 C_L V_{DD}^2 = C_L V_{DD}^2

Step 5 — Average dynamic power at switching frequency ff (activity factor α\alpha): Pavg=αCLVDD2fP_{avg}=\alpha\, C_L V_{DD}^2 f

WHY is the frequency term gone? Because PDP measures per-event energy, not power-over-time. We deliberately removed the "how often" so that speed-cheating doesn't help you.

Figure — Power-delay product

Why PDP alone isn't enough → EDP


Worked Examples


Common Mistakes (Steel-manned)


Recall Feynman: explain to a 12-year-old

Imagine filling a water balloon at a tap. Every time you fill it and pop it, you use a fixed cup of water — no matter how fast or slow you open the tap. That "cup per pop" is the Power-Delay Product: the fixed energy per flip of a logic gate. Turning the tap gently (low voltage) uses less water per pop, but it takes longer to fill. Turning it hard is fast but wastes more. PDP tells you the size of the cup; EDP also cares about how long you waited.


Active Recall

What quantity does PDP physically represent?
The energy dissipated per switching event (unit: joules).
Give the clean formula for PDP of a CMOS gate per transition.
12CLVDD2\tfrac12 C_L V_{DD}^2.
Why is frequency absent from PDP?
PDP is per-event energy, not power-over-time; removing frequency prevents speed from artificially improving the metric.
How much energy does the supply deliver to charge CLC_L to VDDV_{DD}?
CLVDD2C_L V_{DD}^2 (half stored, half burned in PMOS).
Why is half the charging energy lost regardless of resistance?
The 12CLVDD2\tfrac12 C_L V_{DD}^2 dissipated depends only on CLC_L and VDDV_{DD}; resistance changes only the time, not total energy.
What metric fixes PDP's blindness to slow gates?
EDP = Energy-Delay Product = Pavgtp2P_{avg}\,t_p^2.
If VDDV_{DD} halves, how does PDP change?
It drops to one-quarter (PDP VDD2\propto V_{DD}^2).
Units of PDP?
Joules (energy), since W × s = J.
Average dynamic power formula?
Pavg=αCLVDD2fP_{avg}=\alpha C_L V_{DD}^2 f.

Connections

Concept Map

resolved by

defined as

unit joules

explains why

energy from supply

half stored half burned

per transition

independent of

makes it

loophole lower V_DD

motivates

Speed vs Power tug-of-war

Power-Delay Product

PDP equals P_avg times t_p

Energy per switching event

Power equals E over t

Load capacitor C_L charging

E_supply equals C_L V_DD squared

E_cycle equals C_L V_DD squared

PDP equals half C_L V_DD squared

Frequency and delay removed

Honest fair metric

Gate becomes slow

Energy-Delay Product

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, har CMOS gate ke saath ek trade-off hota hai: agar tum use fast banaoge to zyada power lagegi, aur low power chahiye to gate slow ho jaata hai. Isko fairly compare karne ke liye hum Power-Delay Product (PDP) use karte hain — matlab power multiply delay. Iski unit joule hai, kyunki power (watt) × time (second) = energy. Simple baat: PDP batata hai ki ek switching (flip) me kitni energy kharch hoti hai.

First principle se: jab output 0 se VDDV_{DD} tak charge hota hai, supply se CLVDD2C_L V_{DD}^2 energy aati hai. Isme se aadhi capacitor me store hoti hai (12CLVDD2\tfrac12 C_L V_{DD}^2) aur aadhi PMOS resistance me heat ban jaati hai. Discharge pe stored wali bhi NMOS se burn ho jaati hai. Isliye ek transition ka clean PDP hota hai 12CLVDD2\tfrac12 C_L V_{DD}^2. Mazedaar baat — ye formula me na frequency hai na delay, isliye koi speed ka "cheating" karke metric improve nahi kar sakta.

Ek dhyaan dene waali baat: PDP ko sirf VDDV_{DD} kam karke chhota kar sakte ho (kyunki VDD2V_{DD}^2 term hai), lekin phir gate slow ho jayega. Yahi PDP ki kamzori hai. Isliye hum EDP = PDP × delay bhi dekhte hain, jo slow gate ko punish karta hai. Exam me hamesha units check karo (PDP joule hota hai, watt nahi) aur yaad rakho ki charging me hamesha aadhi energy heat banti hai, chahe resistance kuch bhi ho.

Go deeper — visual, from zero

Test yourself — CMOS Circuit Design

Connections