WHY does multiplying power by delay give energy?
Power is energy-per-second (P=E/t). If a gate takes tp seconds to switch, then the energy for that one switch is E=P×tp. So PDP is not an arbitrary "figure of merit" — it is a real physical quantity: the energy the circuit pays each time it flips.
We derive the dynamic energy of a CMOS gate charging a load capacitor CL.
Step 1 — Charge the capacitor from 0 to VDD.Why this step? A CMOS output rising to logic-1 means the PMOS network pulls CL up to VDD. The energy drawn from the supply is what we must account for.
Charge delivered: Q=CLVDD.
Energy drawn from supply during a full charge:
Esupply=∫0∞VDDi(t)dt=VDD∫0∞idt=VDDQ=CLVDD2
Step 2 — Where does that energy go?Why this step? Energy must be conserved; half is stored, half is burned.
Energy stored on the capacitor: Ecap=21CLVDD2.
Energy dissipated in the PMOS resistance while charging: Esupply−Ecap=21CLVDD2.
Step 3 — Discharge (output falls to 0).Why this step? When output goes 1→0, the stored 21CLVDD2 is dumped through the NMOS and burned as heat.
Step 4 — Energy per full cycle (one up + one down):Ecycle=21CLVDD2+21CLVDD2=CLVDD2
Step 5 — Average dynamic power at switching frequency f (activity factor α):
Pavg=αCLVDD2f
WHY is the frequency term gone? Because PDP measures per-event energy, not power-over-time. We deliberately removed the "how often" so that speed-cheating doesn't help you.
Imagine filling a water balloon at a tap. Every time you fill it and pop it, you use a fixed cup of water — no matter how fast or slow you open the tap. That "cup per pop" is the Power-Delay Product: the fixed energy per flip of a logic gate. Turning the tap gently (low voltage) uses less water per pop, but it takes longer to fill. Turning it hard is fast but wastes more. PDP tells you the size of the cup; EDP also cares about how long you waited.
Dekho, har CMOS gate ke saath ek trade-off hota hai: agar tum use fast banaoge to zyada power lagegi, aur low power chahiye to gate slow ho jaata hai. Isko fairly compare karne ke liye hum Power-Delay Product (PDP) use karte hain — matlab power multiply delay. Iski unit joule hai, kyunki power (watt) × time (second) = energy. Simple baat: PDP batata hai ki ek switching (flip) me kitni energy kharch hoti hai.
First principle se: jab output 0 se VDD tak charge hota hai, supply se CLVDD2 energy aati hai. Isme se aadhi capacitor me store hoti hai (21CLVDD2) aur aadhi PMOS resistance me heat ban jaati hai. Discharge pe stored wali bhi NMOS se burn ho jaati hai. Isliye ek transition ka clean PDP hota hai 21CLVDD2. Mazedaar baat — ye formula me na frequency hai na delay, isliye koi speed ka "cheating" karke metric improve nahi kar sakta.
Ek dhyaan dene waali baat: PDP ko sirf VDD kam karke chhota kar sakte ho (kyunki VDD2 term hai), lekin phir gate slow ho jayega. Yahi PDP ki kamzori hai. Isliye hum EDP = PDP × delay bhi dekhte hain, jo slow gate ko punish karta hai. Exam me hamesha units check karo (PDP joule hota hai, watt nahi) aur yaad rakho ki charging me hamesha aadhi energy heat banti hai, chahe resistance kuch bhi ho.