Power-delay product: Exercises — Hardware deep dive

Intuition How to use this page

Work each problem before opening its solution. The exercises climb five rungs: L1 Recognition (can you spot the right formula?) → L2 Application (plug and chug) → L3 Analysis (compare, scale, reason about trade-offs) → L4 Synthesis (combine PDP with delay and voltage) → L5 Mastery (design-level judgement calls). Every symbol used here is defined in the parent PDP note; if you feel a gap, re-read it first.

The only formulas you need on this page: $PDP = \frac{1}{2} C_{L} V_{D D}^{2}, E_{cy c l e} = C_{L} V_{D D}^{2}, P_{a v g} = α C_{L} V_{D D}^{2} f, EDP = PDP \times t_{p}$ where $C_{L}$ is the load capacitance (in farads, F), $V_{D D}$ is the supply voltage (in volts, V), $f$ is the switching frequency (in hertz, Hz), $α$ is the activity factor (a dimensionless number between 0 and 1 counting how often a node actually flips), and $t_{p}$ is the propagation delay (in seconds, s).

Recall Unit refresher (open if "fF", "pJ", "μW" scare you)

A femto (f) means $1 0^{- 15}$ , pico (p) means $1 0^{- 12}$ , nano (n) means $1 0^{- 9}$ , micro (μ) means $1 0^{- 6}$ . So $10 fF = 10 \times 1 0^{- 15} F$ , and $5 fJ = 5 \times 1 0^{- 15}$ joules. Energy in joules (J) = power in watts (W) × time in seconds (s). That single fact powers every check below.

Level 1 — Recognition

Goal: recognise which quantity a formula produces, and read its units correctly.

Recall Solution 1.1

Answer: (b). What each option is:

(a) $C_{L} V_{D D}^{2}$ is the energy for a full up+down cycle (charge and discharge).
(b) $\frac{1}{2} C_{L} V_{D D}^{2}$ is half of that — one transition. This is the PDP.
(c) $α C_{L} V_{D D}^{2} f$ has an $f$ (per second) in it, so it is a power (watts), not an energy.
(d) $\frac{1}{2} C_{L} V_{D D}$ has units of coulombs·volts... no — actually farad·volt = coulomb, times volt = charge×volt is energy, but the square is missing so it is dimensionally wrong for our derivation (it drops a factor of $V_{D D}$ ). Not the PDP.

The clean per-transition energy is $\frac{1}{2} C_{L} V_{D D}^{2}$ .

Recall Solution 1.2

PDP = power × time = W × s = joules (J) — an energy. The name starts with "Power" but the product with time cancels the "per-second," leaving pure energy.

Recall Solution 1.3

PDP. Femtojoules are an energy measured per operation — exactly the definition of PDP. EDP would carry units of J·s; average power would be in watts.

Level 2 — Application

Goal: substitute numbers correctly, tracking powers of ten.

Recall Solution 2.1

Step 1 — pick the formula. Why? We want energy per single transition ⇒ $PDP = \frac{1}{2} C_{L} V_{D D}^{2}$ . Step 2 — substitute. $PDP = \frac{1}{2} (20 \times 1 0^{- 15}) (1.2)^{2}$ Step 3 — arithmetic. $(1.2)^{2} = 1.44$ . Then $\frac{1}{2} \times 20 \times 1.44 = 14.4$ , carrying $1 0^{- 15}$ : $PDP = 14.4 \times 1 0^{- 15} J = 14.4 fJ$

Recall Solution 2.2

Step 1 — formula. Why? We want power over time at a given frequency ⇒ $P_{a v g} = α C_{L} V_{D D}^{2} f$ . Step 2 — substitute. $P_{a v g} = (0.5) (20 \times 1 0^{- 15}) (1.2)^{2} (2 \times 1 0^{9})$ Step 3 — arithmetic. $C_{L} V_{D D}^{2} = 20 \times 1 0^{- 15} \times 1.44 = 2.88 \times 1 0^{- 14}$ . Times $f = 2 \times 1 0^{9}$ gives $5.76 \times 1 0^{- 5}$ . Times $α = 0.5$ : $P_{a v g} = 2.88 \times 1 0^{- 5} W = 28.8 μ W$

Recall Solution 2.3

Step 1 — supply energy. Why? From the parent derivation, charging draws $E_{s u ppl y} = C_{L} V_{D D}^{2}$ (not half — the half only appears when we split stored vs burned). $E_{s u ppl y} = 20 \times 1 0^{- 15} \times 1.44 = 2.88 \times 1 0^{- 14} J = 28.8 fJ$ Step 2 — split. Half stored, half burned: $E_{s t or e d} = E_{b u r n e d} = \frac{1}{2} C_{L} V_{D D}^{2} = 14.4 fJ each .$ Notice $E_{s t or e d}$ equals the PDP from Exercise 2.1 — the stored charge is the per-transition energy.

Level 3 — Analysis

Goal: reason about how PDP responds when you scale a parameter.

Recall Solution 3.1

Step 1 — spot the dependence. Why? $PDP = \frac{1}{2} C_{L} V_{D D}^{2}$ , so with $C_{L}$ fixed, PDP $\propto V_{D D}^{2}$ . Step 2 — ratio. $\frac{PDP _{n e w}}{PDP _{o l d}} = (\frac{0.8}{1.0})^{2} = 0.64.$ Step 3 — interpret. New PDP is $64%$ of old ⇒ a $36% reduction$ . A $20%$ voltage cut buys a $36%$ energy cut — the square makes voltage the most powerful lever.

Recall Solution 3.2

Step 1 — PDP of each. Why? PDP $= \frac{1}{2} C_{L} V_{D D}^{2}$ contains no $t_{p}$ , so delay drops out. $PDP_{A} = PDP_{B} = \frac{1}{2} (10 \times 1 0^{- 15}) (1.0)^{2} = 5 fJ .$ Step 2 — verdict. They are equal at 5 fJ. Step 3 — why PDP is blind here. Because PDP measures energy per flip and both flip using the same $C_{L}$ and $V_{D D}$ , it literally cannot see that B is twice as slow. To reward A's speed you must fold delay back in with EDP (next level).

Recall Solution 3.3

(a) Energy burned: unchanged at $\frac{1}{2} C_{L} V_{D D}^{2}$ . Why? The dissipated energy depends only on $C_{L}$ and $V_{D D}$ , not on the path resistance — a classic RC result. A bigger $R$ just spreads the same total loss over a longer time. (b) Time: the charging time constant is $τ = R C_{L}$ , so doubling $R$ doubles $τ$ — the gate charges twice as slowly. See the figure: same shaded loss area, stretched wider in time.

Level 4 — Synthesis

Goal: combine PDP, delay, voltage scaling, and EDP into one decision.

Recall Solution 4.1

Step 1 — formula. $EDP = PDP \times t_{p}$ . Why? EDP re-inserts delay so slow gates are penalised. Step 2 — substitute. $EDP = (5 \times 1 0^{- 15} J) (50 \times 1 0^{- 12} s) = 250 \times 1 0^{- 27} = 2.5 \times 1 0^{- 25} J\cdots$ Note the unit J·s (joule-seconds) — the "s" makes clear this metric cares about time.

Recall Solution 4.2

Step 1 — new PDP. PDP $\propto V_{D D}^{2}$ : $PDP_{n e w} = 5 fJ \times (0.7)^{2} = 5 \times 0.49 = 2.45 fJ (- 51%) .$ Step 2 — delay scaling factor. Why? Lower $V_{D D}$ moves the transistor closer to $V_{t h}$ , weakening drive. $\frac{t _{p, n e w}}{t _{p, o l d}} = \frac{V _{D D, n e w} / ( V _{D D, n e w} - V _{t h} ) ^{2}}{V _{D D, o l d} / ( V _{D D, o l d} - V _{t h} ) ^{2}} = \frac{0.7/ ( 0.5 ) ^{2}}{1.0/ ( 0.8 ) ^{2}} = \frac{0.7/0.25}{1.0/0.64} = \frac{2.8}{1.5625} = 1.792.$ So $t_{p, n e w} = 50 ps \times 1.792 = 89.6 ps$ — nearly 1.8× slower. Step 3 — old and new EDP. $EDP_{o l d} = 5 fJ \times 50 ps = 2.5 \times 1 0^{- 25} J\cdots .$ $EDP_{n e w} = 2.45 fJ \times 89.6 ps = 219.5 \times 1 0^{- 27} = 2.195 \times 1 0^{- 25} J\cdots .$ Step 4 — verdict. EDP dropped from $2.5$ to $2.195 \times 1 0^{- 25}$ J·s (about $- 12%$ ), so scaling was a modest win on EDP — energy fell more than delay grew, this time. But notice how thin the margin is: PDP alone claimed a $51%$ improvement; EDP reveals only $\approx 12%$ once slowness is charged for. Always check EDP before celebrating a voltage cut.

Recall Solution 4.3

Step 1 — energy per cycle. Why? $P = E_{cy c l e} \times f$ when a cycle happens every clock tick at $α = 1$ , so $E_{cy c l e} = P / f$ . $E_{cy c l e} = \frac{40 \times 1 0 ^{- 6}}{1 \times 1 0 ^{9}} = 40 \times 1 0^{- 15} = 40 fJ .$ Step 2 — PDP is half. One cycle = up + down = two transitions; PDP is per transition: $PDP = \frac{1}{2} E_{cy c l e} = 20 fJ .$

Level 5 — Mastery

Goal: judgement calls where the naive metric misleads and you must pick the right tool.

Recall Solution 5.1

Step 1 — EDPs. $EDP_{X} = 3 fJ \times 200 ps = 600 \times 1 0^{- 27} = 6.0 \times 1 0^{- 25} J\cdots .$ $EDP_{Y} = 4 fJ \times 60 ps = 240 \times 1 0^{- 27} = 2.4 \times 1 0^{- 25} J\cdots .$ By EDP, Y wins (lower is better) because it is much faster. Step 2 — but read the requirement. The clock is slow; delay is never the bottleneck. Speed you can't use is worthless here, while every joule drains the battery. Step 3 — pick the right metric. For a battery-limited, delay-slack system the honest metric is PDP (energy per op), not EDP. By PDP, $3 fJ < 4 fJ$ , so choose Adder X. Verdict: EDP said Y, PDP said X — choose X. The lesson: EDP is only the right yard-stick when delay actually matters. Match the metric to the constraint.

Recall Solution 5.2

Step 1 — effect of shrinking $C_{L}$ . PDP $\propto C_{L}$ ⇒ energy falls linearly. Delay $\propto C_{L}$ ⇒ delay also falls. So shrinking $C_{L}$ is a double win: less energy and faster. Step 2 — effect of lowering $V_{D D}$ . PDP $\propto V_{D D}^{2}$ ⇒ energy falls fast (good). But delay $\propto V_{D D} / (V_{D D} - V_{t h})^{2}$ rises as $V_{D D} \to V_{t h}$ (bad). Step 3 — verdict. Shrinking $C_{L}$ is the strictly better lever: it improves PDP and delay and therefore EDP. Voltage scaling trades delay for energy. When you can, cut capacitance first, then use $V_{D D}$ scaling only to reach your remaining energy target within timing slack.

Recall Solution 5.3

Algebra. Average power is $P_{a v g} = α C_{L} V_{D D}^{2} f$ . Multiply by delay $t_{p}$ ... no — instead form energy per transition directly: $PDP = \frac{E _{cy c l e}}{2} = \frac{C _{L} V _{D D}^{2}}{2} .$ There is no $f$ on the right-hand side. Frequency only ever entered $P_{a v g}$ through "how many times per second," which is precisely what dividing by "number of events" removes. Physical reason. Each flip pours out a fixed "cup" of energy $\frac{1}{2} C_{L} V_{D D}^{2}$ (independent of $R$ , and independent of how often you flip). Power = cups-per-second scales with $f$ ; energy-per-cup does not. That frequency-independence is exactly why PDP is an honest, speed-cheat-proof metric — the whole point of the parent note.

Connections

Power-delay product (parent)
Dynamic power dissipation
CMOS Inverter
Propagation delay
Energy-delay product (EDP)
Voltage scaling / DVFS
Switching activity factor
RC charging energy

Exercises — Power-delay product

Level 1 — Recognition

Level 2 — Application

Level 3 — Analysis

Level 4 — Synthesis

Level 5 — Mastery

Connections

Solution-strategy Map