Power-delay product: Worked examples — Hardware deep dive

Quick symbol refresher (so line one makes sense):

$C_{L}$ = the load capacitance the gate must charge, measured in farads (F). Think "size of the bucket."
$V_{D D}$ = the supply voltage in volts (V) — the "water pressure."
$PDP = \frac{1}{2} C_{L} V_{D D}^{2}$ = energy per single 0→1 or 1→0 transition, in joules (J).
$E_{cy c l e} = C_{L} V_{D D}^{2}$ = energy the supply spends over a full up-then-down cycle (twice PDP).
$P_{a v g} = α C_{L} V_{D D}^{2} f$ = average dynamic power in watts (W), where $α$ is the activity factor (fraction of clocks that actually flip) and $f$ is clock frequency in hertz (Hz).
$t_{p}$ = propagation delay, seconds per transition.
$EDP = PDP \times t_{p}$ = Energy-Delay Product, units J·s.

Unit prefixes you will meet: $f = 1 0^{- 15}$ (femto), $p = 1 0^{- 12}$ (pico), $n = 1 0^{- 9}$ (nano), $μ = 1 0^{- 6}$ (micro), $G = 1 0^{9}$ (giga).

The scenario matrix

Every PDP problem is really one of these case classes. The rest of the page fills each cell.

#	Case class	What makes it tricky	Covered by
A	Plain per-transition PDP	picking the right formula	Ex 1
B	Power×delay cross-check	proving the two paths agree	Ex 2
C	Voltage scaling (sign of change)	$V^{2}$ law, energy drops	Ex 3
D	Zero / degenerate input	$V_{D D} = 0$ or $C_{L} = 0$ → PDP $= 0$	Ex 4
E	Limiting behaviour	$V_{D D} \to 0$ makes delay blow up	Ex 5
F	Full-cycle vs per-transition convention	factor-of-2 trap	Ex 6
G	Real-world word problem	battery life from PDP	Ex 7
H	Exam twist: which of two gates wins?	PDP ties, EDP breaks it	Ex 8
I	Activity factor $α < 1$	idle bits don't burn energy	Ex 9

Example 1 — Cell A: plain per-transition PDP

Worked example Statement

An inverter drives $C_{L} = 8 fF$ from a supply $V_{D D} = 1.2 V$ . Find the energy per switching transition.

Forecast: guess — will the answer be a few femtojoules, or thousands? (Bucket is tiny, pressure is ~1 V, so expect single-digit fJ.)

Step 1 — choose the formula $PDP = \frac{1}{2} C_{L} V_{D D}^{2}$ . Why this step? We are asked for energy per single flip, not a full cycle and not power. The clean textbook PDP is exactly the per-transition energy, and it needs no frequency or delay.

Step 2 — substitute the numbers. $PDP = \frac{1}{2} (8 \times 1 0^{- 15}) (1.2)^{2} = \frac{1}{2} (8 \times 1 0^{- 15}) (1.44)$ Why this step? Just arithmetic — square the voltage first (because energy scales with $V^{2}$ , see RC charging energy), then multiply by capacitance and the one-half.

Step 3 — evaluate. $PDP = 5.76 \times 1 0^{- 15} J = 5.76 fJ .$

Verify: Units: $F \cdot V^{2} = C/V \cdot V^{2} = C \cdot V = J$ ✓ (charge times voltage is energy). Magnitude is a few fJ, matching the forecast.

Example 2 — Cell B: cross-check via power × delay

Worked example Statement

The Example 1 inverter ( $C_{L} = 8 fF$ , $V_{D D} = 1.2 V$ ) toggles every clock at $f = 2 GHz$ with activity $α = 1$ . Show the power×delay route gives the same per-transition energy.

Forecast: we should recover $5.76$ fJ per transition (never trust a "cross-check" that disagrees with itself).

Step 1 — average dynamic power. $P_{a v g} = α C_{L} V_{D D}^{2} f = 1 \cdot (8 \times 1 0^{- 15}) (1.44) (2 \times 1 0^{9}) .$ Why this step? Dynamic power is energy-per-cycle times cycles-per-second. Here $α = 1$ so every clock flips.

Step 2 — evaluate power. $P_{a v g} = 8 \times 1 0^{- 15} \times 1.44 \times 2 \times 1 0^{9} = 2.304 \times 1 0^{- 5} W = 23.04 μ W .$

Step 3 — energy per full cycle $= P_{a v g} / f$ . $E_{cy c l e} = \frac{2.304 \times 1 0 ^{- 5}}{2 \times 1 0 ^{9}} = 1.152 \times 1 0^{- 14} J = 11.52 fJ = C_{L} V_{D D}^{2} .$ Why this step? Dividing power by frequency undoes the "per second," leaving energy per cycle. A full cycle is up and down.

Step 4 — per transition = half a cycle $= 11.52/2 = 5.76$ fJ. Why this step? One cycle = two transitions, so PDP is exactly half of $E_{cy c l e}$ .

Verify: $5.76$ fJ matches Example 1 exactly ✓. Two independent routes, same energy — that's the whole point of PDP being an honest per-event number.

Example 3 — Cell C: voltage scaling, energy drops

Example 4 — Cell D: zero / degenerate input

Worked example Statement

(a) A powered-down block has $V_{D D} = 0$ . (b) A gate whose output is left floating with $C_{L} = 0$ . What is PDP in each case, and why does it make physical sense?

Forecast: both should give zero dynamic energy — no pressure or no bucket means nothing to fill.

Step 1 — case (a), $V_{D D} = 0$ . $PDP = \frac{1}{2} C_{L} (0)^{2} = 0.$ Why this step? With zero supply there is no voltage to charge the cap to; no charge moves, no energy is spent. This is the physical basis of power-gating.

Step 2 — case (b), $C_{L} = 0$ . $PDP = \frac{1}{2} (0) V_{D D}^{2} = 0.$ Why this step? With no capacitance there is nothing to store charge; the node snaps instantly with zero energy (idealised — real wires always add some $C_{L}$ ).

Verify: Both zero, and neither blows up or goes negative — PDP is a product of a positive $\frac{1}{2}$ , a non-negative $C_{L}$ , and a squared (hence non-negative) voltage, so PDP $\geq 0$ always ✓. Energy can't be negative; the formula respects that.

Example 5 — Cell E: limiting behaviour as $V_{D D} \to 0$

Worked example Statement

Using the delay model from the parent note $t_{p} \propto \frac{V _{D D}}{( V _{D D} - V _{t h} ) ^{2}}$ with threshold $V_{t h} = 0.4 V$ , describe what happens to PDP and delay as $V_{D D}$ shrinks toward $V_{t h}$ . Compute the delay ratio between $V_{D D} = 1.2 V$ and $V_{D D} = 0.5 V$ .

Forecast: PDP keeps shrinking (good), but delay should explode as $V_{D D} \to V_{t h}$ (bad). Expect a large delay-ratio.

Step 1 — the two limits qualitatively. See the figure below.

Why this step? We need the geometry: PDP is a smooth parabola $\to 0$ , while delay has a pole at $V_{D D} = V_{t h}$ (denominator $\to 0$ ). The red delay curve shoots to infinity right where the orange energy curve is still falling — that's the whole DVFS danger.

Step 2 — delay ratio. Since only the shape matters, form $\frac{t _{p} ( 0.5 )}{t _{p} ( 1.2 )} = \frac{0.5/ ( 0.5 - 0.4 ) ^{2}}{1.2/ ( 1.2 - 0.4 ) ^{2}} = \frac{0.5/0.01}{1.2/0.64} .$ Why this step? The proportionality constant cancels in a ratio, so we can compare delays without knowing it.

Step 3 — evaluate. $= \frac{50}{1.875} = 26.67.$

Verify: Dropping to $0.5$ V makes the gate ~ $26.7 \times$ slower while PDP only drops by $(0.5/1.2)^{2} \approx 0.174$ (to ~17% of original). Slowness grew far faster than energy shrank — exactly why raw PDP is a "loophole" metric and EDP exists. Units of the ratio are dimensionless ✓.

Example 6 — Cell F: full-cycle vs per-transition trap

Worked example Statement

A datasheet says "energy per operation = $12 fJ$ " for a gate with $C_{L} = ?$ at $V_{D D} = 1.0 V$ . A student reads this as PDP $= 12$ fJ and back-solves $C_{L}$ . Where is the factor-of-two trap, and what is $C_{L}$ under each convention?

Forecast: the answer differs by exactly $2 \times$ depending on whether "per operation" means one transition (PDP) or a full up+down cycle.

Step 1 — per-transition reading (PDP convention). $12 fJ = \frac{1}{2} C_{L} (1.0)^{2} \Rightarrow C_{L} = 24 fF .$ Why this step? If "operation" = one flip, use $\frac{1}{2} C_{L} V_{D D}^{2}$ and solve for $C_{L}$ .

Step 2 — full-cycle reading. $12 fJ = C_{L} (1.0)^{2} \Rightarrow C_{L} = 12 fF .$ Why this step? If "operation" = a complete cycle, the energy is $C_{L} V_{D D}^{2}$ with no half.

Verify: $24/12 = 2$ ✓ — the ambiguity is exactly the factor of two the parent note's [!mistake] warned about. Always confirm which convention a source uses before back-solving.

Example 7 — Cell G: real-world battery-life word problem

Worked example Statement

A sensor chip performs $3 \times 1 0^{9}$ switching transitions per second, each costing PDP $= 5.76 fJ$ (our Ex 1 gate). It runs off a $0.5 Wh$ coin cell. Ignoring leakage, how long can it run?

Forecast: femtojoules per flip but billions of flips per second — guess the power is tens of microwatts and the battery lasts years.

Step 1 — dynamic power. $P = (transitions/s) \times (energy/transition) = 3 \times 1 0^{9} \times 5.76 \times 1 0^{- 15} .$ Why this step? Power is energy-per-event times events-per-second — the definition of average power.

Step 2 — evaluate power. $P = 1.728 \times 1 0^{- 5} W = 17.28 μ W .$

Step 3 — convert battery energy to joules. $0.5 Wh = 0.5 \times 3600 J = 1800 J .$ Why this step? One watt-hour is one watt for 3600 seconds; joules are the common currency.

Step 4 — lifetime $=$ energy $\div$ power. $t = \frac{1800}{1.728 \times 1 0 ^{- 5}} = 1.0417 \times 1 0^{8} s .$

Step 5 — convert to years. $\frac{1.0417 \times 1 0 ^{8}}{3.156 \times 1 0 ^{7}} \approx 3.30 years .$

Verify: Power ~17 μW matches forecast; lifetime measured in years is exactly what a coin cell running microwatts should give ✓. Units: J ÷ (J/s) = s ✓.

Example 8 — Cell H: exam twist, PDP ties but EDP breaks it

Worked example Statement

Two gate designs have identical PDP $= 5 fJ$ , but Gate X has $t_{p} = 30 ps$ and Gate Y has $t_{p} = 70 ps$ . Which is the better design, and by what EDP margin?

Forecast: identical PDP means neither wins on energy — so the faster one (X) must win once we weigh delay. Expect Y's EDP to be worse by the delay ratio $70/30$ .

Step 1 — why PDP can't decide. $PDP_{X} = PDP_{Y} = 5 fJ .$ Why this step? PDP has no $t_{p}$ in it, so it is blind to the speed difference — this is the "loophole" that motivates EDP.

Step 2 — compute EDP for each. $EDP_{X} = 5 fJ \times 30 ps = 150 fJ\cdotps, EDP_{Y} = 5 fJ \times 70 ps = 350 fJ\cdotps .$ Why this step? EDP $= PDP \times t_{p}$ multiplies energy by delay, so a slow gate is penalised.

Step 3 — ratio. $\frac{EDP _{Y}}{EDP _{X}} = \frac{350}{150} = \frac{7}{3} \approx 2.33.$

Verify: Gate X wins; Y's EDP is $2.33 \times$ worse — exactly the delay ratio $70/30$ since energies are equal ✓. Lower EDP is better, so X is the design to ship.

Example 9 — Cell I: activity factor below one

Worked example Statement

A bus of the Ex 1 gates ( $C_{L} = 8 fF$ , $V_{D D} = 1.2 V$ ) runs at $f = 1 GHz$ but only flips on 20% of clock cycles, i.e. activity $α = 0.2$ . Find the average power. Compare with $α = 1$ .

Forecast: most cycles are idle, so power should be one-fifth of the $α = 1$ case.

Step 1 — average power with $α$ . $P = α C_{L} V_{D D}^{2} f = 0.2 \times (8 \times 1 0^{- 15}) (1.44) (1 \times 1 0^{9}) .$ Why this step? $α$ scales dynamic power linearly because idle cycles charge nothing — only real flips cost energy.

Step 2 — evaluate. $P = 0.2 \times 8 \times 1 0^{- 15} \times 1.44 \times 1 0^{9} = 2.304 \times 1 0^{- 6} W = 2.304 μ W .$

Step 3 — compare with full activity. At $α = 1$ : $P = 11.52 μ W$ . Ratio $= 0.2$ . Why this step? Confirms the linear scaling — cutting activity to 20% cuts dynamic power to 20%.

Verify: $2.304/11.52 = 0.2 = α$ ✓. Note the PDP per transition is unchanged at $5.76$ fJ — $α$ affects power (how often you pay), never the energy of one flip (the size of each payment) ✓.

Recall Which formula for which cell?

Per single flip energy ::: $PDP = \frac{1}{2} C_{L} V_{D D}^{2}$ Full up+down cycle energy ::: $E_{cy c l e} = C_{L} V_{D D}^{2}$ (twice PDP) Average dynamic power ::: $P_{a v g} = α C_{L} V_{D D}^{2} f$ Breaks a PDP tie between two speeds ::: $EDP = PDP \times t_{p}$ Effect of halving $V_{D D}$ on PDP ::: PDP → one quarter (the $V^{2}$ law) Effect of $α$ on the energy of one transition ::: none — $α$ only scales power, not per-flip energy

Connections

← Back to parent: Power-Delay Product
Dynamic power dissipation
CMOS Inverter
Propagation delay
Energy-delay product (EDP)
Voltage scaling / DVFS
Switching activity factor
RC charging energy