Question bank — Power-delay product

False. PDP = power $\times$ time = W$\cdot$s = joules, i.e. energy. The name describes its two factors, not its unit.

False. As derived in the legend, $P_{avg}=\frac{1}{2}{C}_L{V}_{DD}^2/t_p$, so the $t_p$ cancels exactly on multiplication, leaving pure per-transition energy with no time in it.

False. PDP $\propto V_{DD}^2$, so halving voltage drops it to one quarter, not one half — this is why Voltage scaling / DVFS is so attractive for energy.

False. Faster usually means more power, and the clean PDP $\frac{1}{2}{C}_L{V}_{DD}^2$ has no $t_p$ at all — the product stays put. Only EDP rewards speed.

False. The supply delivers the full $C_L{V}_{DD}^2$; only half of that ends up stored on the cap, the other half is burned charging it.

False. The dissipated $\frac{1}{2}{C}_L{V}_{DD}^2$ depends only on $C_L$ and $V_{DD}$; resistance changes the time to charge, never the total heat — a core RC charging energy result.

True. Because PDP is energy per transition, it strips out how often you switch, so you cannot cheat by slowing the clock down.

False. EDP multiplies by an extra $t_p$, so a low-energy-but-slow design can win on PDP yet lose on EDP.

False. PDP $=\frac{1}{2}{C}_L{V}_{DD}^2$ is purely the dynamic switching component; static leakage flows even with no transition and is a separate budget entirely.

Two slips. First, back-to-back switching gives $f\approx 1/(2t_p)$ (a period holds two transitions), not $1/t_p$. Second, per the event legend PDP is defined per transition, so the correct value is the half, $\frac{1}{2}{C}_L{V}_{DD}^2$; $C_L{V}_{DD}^2$ is the per-cycle energy.

PDP contains no $f$ — it is per-transition energy. Lowering $f$ cuts power and throughput, not the energy paid each flip.

The other half is dissipated as heat in the pull-up device during the charge, so a single rise is only 50% efficient at delivering energy to the cap.

More transistors typically raise the load/self capacitance $C_L$, and PDP scales linearly with $C_L$, so it does change.

Dimensionally wrong: PDP already equals $P_{avg}{t}_p$, so EDP $=P_{avg}{t}_p\times t_p=P_{avg}{t}_p^2$.

PDP is about dynamic switching energy per transition, not static/leakage power — an idle gate performs no transition, so its dynamic PDP contribution is zero.

The clean $\frac{1}{2}{C}_L{V}_{DD}^2$ is only the capacitive charging component; the brief PMOS-and-NMOS-both-on short-circuit energy is an additional per-transition term not in that formula.

Step 1: one transition takes $t_p$, so $P_{avg}=E_{tr}/t_p$. Step 2: multiply by $t_p$: $P_{avg}\cdot t_p=E_{tr}$. Step 3: the $t_p$ cancels, leaving energy-per-event — deliberately, so Propagation delay speed can't game the metric.

Step 1: raw power drops if you simply switch less often. Step 2: PDP normalizes to a single transition. Step 3: the "how often" trick is removed, exposing the true energy each flip costs.

Step 1: PDP $\propto V_{DD}^2$, so lowering $V_{DD}$ always shrinks it. Step 2: but delay $\propto V_{DD}/(V_{DD}-V_{th}{)}^2$ blows up. Step 3: EDP's extra $t_p^2$ penalizes that slowness, rewarding designs both low-energy and fast.

Step 1: dissipation is $\int i^{2}Rdt$ over the RC charge. Step 2: larger $R$ means smaller $i$ but proportionally longer time. Step 3: the two effects cancel, giving a fixed $\frac{1}{2}{C}_L{V}_{DD}^2$ with $R$ absent.

Step 1: charge moved is $Q=C_L{V}_{DD}$ (one factor of $V_{DD}$). Step 2: each charge is pushed through a potential of order $V_{DD}$ (second factor). Step 3: energy $\frac{1}{2}{C}_L{V}_{DD}^2$ picks up $V_{DD}$ from each — a strong Voltage scaling / DVFS lever.

Step 1: $\alpha$ counts how often per clock a flip happens (a rate). Step 2: PDP measures one transition's cost. Step 3: the rate is already normalized away, so $\alpha$ has nothing to multiply.

The formula $\frac{1}{2}{C}_L{V}_{DD}^2$ still describes the cost if a transition occurred, but with zero transitions the dynamic energy actually spent is zero — PDP characterizes a potential event, not idle behavior (idle drain is leakage, a separate budget).

No. Using the stated delay model $t_p\propto V_{DD}/(V_{DD}-V_{th}{)}^2$, as $V_{DD}\to V_{th}$ the denominator vanishes and delay blows up — PDP looks perfect but EDP explodes, so the gate is useless.

PDP $\to 0$ since it scales linearly with $C_L$; a driverless, unloaded node ideally costs no dynamic switching energy — real gates still have parasitic self-capacitance, so it never truly hits zero.

Per the event legend, a full cycle is two transitions, so it costs $C_L{V}_{DD}^2$; PDP (per transition) is the half. Always confirm whether a problem counts transitions or cycles.

Yes — each partial charge/discharge burns real dynamic energy even if the logic value is ultimately unchanged, which is why glitch power is a genuine drain not captured by counting useful transitions.