Static vs dynamic power dissipation

1. The big picture

$P_{\text{total}} = \underbrace{P_{\text{switching}} + P_{\text{short-circuit}}}_{\text{dynamic}} + \underbrace{P_{\text{static}}}_{\text{leakage}}$

• WHAT each term is: switching = charging load caps; short-circuit = both transistors briefly on during a transition; static = leakage while idle.
• HOW they differ: dynamic scales with activity (how often you switch) and frequency; static flows always, independent of switching.

2. Dynamic switching power — derived from scratch

WHY it exists: every wire + gate input has capacitance. To make the output go HIGH you must dump charge onto $C_L$; to make it LOW you drain that charge to ground. Both cost energy.

Derivation — energy per rising transition. When the PMOS turns on, the supply $V_{DD}$ charges $C_L$ from $0$ to $V_{DD}$.

Energy drawn from the supply: $E_{\text{supply}} = \int_0^{\infty} V_{DD}\, i(t)\, dt = V_{DD}\int_0^{\infty} C_L \frac{dV_{out}}{dt}\, dt = V_{DD} C_L \int_0^{V_{DD}} dV_{out} = C_L V_{DD}^2$

Why this step? Current into the cap is $i = C_L\, dV_{out}/dt$; substituting turns a time integral into a voltage integral, and the voltage limits are $0 \to V_{DD}$.

Energy actually stored on the capacitor at the end: $E_{\text{stored}} = \int_0^{V_{DD}} V_{out}\, i\, dt = C_L\int_0^{V_{DD}} V_{out}\, dV_{out} = \tfrac{1}{2} C_L V_{DD}^2$

So half the supply energy is stored, the other half $\tfrac12 C_L V_{DD}^2$ is burned as heat in the PMOS resistance. On the falling edge the stored $\tfrac12 C_L V_{DD}^2$ is dumped through the NMOS as heat.

From energy to power. If the gate makes $f$ complete cycles per second: $P_{\text{switching}} = C_L V_{DD}^2 f$

Real circuits don't toggle every clock. Introduce the activity factor $\alpha$ = probability a node makes a rising transition per clock:

3. Short-circuit power

WHY: the input ramps through the region $V_{Tn} < V_{in} < V_{DD}-|V_{Tp}|$ where neither transistor is fully off. A pulse of current $I_{sc}$ flows straight through.

$P_{\text{sc}} \approx \alpha\, f\, \bar{I}_{sc}\, V_{DD} \, t_{sc}$ where $t_{sc}$ is proportional to input rise/fall time. HOW to reduce: keep edges sharp (fast transitions) — slow inputs widen the crowbar window. Usually 5–15% of dynamic power.

4. Static (leakage) power — from scratch

$\boxed{P_{\text{static}} = I_{\text{leak}}\, V_{DD}}$

Main leakage sources (WHAT):

1. Subthreshold leakage — a transistor "off" ($V_{GS}<V_T$) still passes a small current that grows exponentially as $V_T$ shrinks: $I_{sub} \propto e^{\,(V_{GS}-V_T)/(nV_{th})}, \qquad V_{th}=\tfrac{kT}{q}\approx 26\text{ mV at }300\text{K}$ WHY it matters: as chips scaled, engineers lowered $V_T$ for speed — which blew up $I_{sub}$ exponentially.
2. Gate-oxide tunneling — electrons quantum-tunnel through ultra-thin gate oxide.
3. Junction / reverse-bias leakage — reverse-biased diode currents.

HOW to fight it: high-$V_T$ transistors, power gating (sleep switches), body biasing, thicker/high-$k$ oxide.

5. Worked examples

6. Common mistakes

7. Forecast-then-Verify

Flashcards

Connections

• CMOS Inverter operation
• Threshold voltage and subthreshold conduction
• Voltage scaling and Dennard scaling
• Power gating and clock gating
• Propagation delay in CMOS
• Capacitance in interconnects

Concept Map

Hinglish (regional understanding)