CMOS NAND and NOR gate design

WHY does CMOS work this way?

WHY complementary? Because if both networks conducted at once we'd get a short-circuit ( $V_{DD}\to GND$ ) burning static power; if neither conducted the output would float and hold garbage. Making PUN and PDN logical duals guarantees exactly-one-conducts.

HOW to build the NAND gate

We want $Y=\overline{A\cdot B}$ .

Step 1 — PDN: $Y=0$ only when $A\cdot B=1$ , i.e. when $A$ AND $B$ are both HIGH. Why this step? AND ⇒ series NMOS. So put two NMOS in series between $Y$ and $GND$ .

Step 2 — PUN (dual): swap series→parallel and NMOS→PMOS. Why this step? $\overline{A\cdot B}=\bar A+\bar B$ , an OR of the complements → parallel PMOS. Two PMOS in parallel between $V_{DD}$ and $Y$ .

Step 3 — verify one input: $A=1,B=0$ . NMOS series broken (B off) ⇒ PDN off. PMOS parallel: the $B$ -PMOS is ON (gate=0) ⇒ PUN pulls $Y=1$ . ✓ Matches $\overline{1\cdot0}=1$ .

Worked example NAND truth verification

A	B	PDN (series N)	PUN (parallel P)	Y
0	0	off	ON (both P)	1
0	1	off	ON (A-P)	1
1	0	off	ON (B-P)	1
1	1	ON	off	0

Exactly one network conducts in every row → no float, no short. ✓

HOW to build the NOR gate

We want $Y=\overline{A+B}$ .

Step 1 — PDN: $Y=0$ when $A+B=1$ , i.e. $A$ OR $B$ HIGH. Why? OR ⇒ parallel NMOS between $Y$ and $GND$ .

Step 2 — PUN (dual): $\overline{A+B}=\bar A\cdot\bar B$ ⇒ AND of complements ⇒ series PMOS between $V_{DD}$ and $Y$ .

Sizing: WHY NAND is preferred over NOR

Recall Feynman: explain to a 12-year-old

Imagine two water pipes. On top, pipes bring water down (that's "1"); on the bottom, drains let water out (that's "0"). Each pipe has a valve controlled by a switch. In a NAND gate, the drain side has two valves in a line — water only escapes if you open both switches. So the output stays "full" (1) unless both inputs are on. The top pipes are arranged the opposite way (side-by-side) so that whenever the drain is blocked, one top pipe is always open to keep it full. It's designed so the tank is never both filling and draining, and never left empty-and-open.

Active Recall

Which transistor type forms the pull-up network and why?

PMOS, because they pass a strong logic 1 (conduct when gate is LOW), pulling output toward

V_{DD}

In a PDN, series NMOS implement which logic operation?

AND (path conducts only if all are ON).

In a PDN, parallel NMOS implement which logic?

OR (any single ON path conducts).

Give the transistor topology of a 2-input NAND.

PDN: 2 NMOS in series; PUN: 2 PMOS in parallel.

Give the transistor topology of a 2-input NOR.

PDN: 2 NMOS in parallel; PUN: 2 PMOS in series.

Why is NAND preferred over NOR in CMOS?

NOR needs slow PMOS in series (must be widened ~

2k

), hurting speed/area; NAND keeps PMOS in parallel.

State the duality rule for building the PUN from the PDN.

Swap NMOS↔PMOS and swap series↔parallel (De Morgan in silicon).

For NAND with A=1,B=0, which network conducts and what is Y?

PUN conducts (B-PMOS on), Y=1.

Why must PUN and PDN be logical duals?

So exactly one conducts per input → no floating output and no

V_{DD}

-to-GND short.

Which De Morgan identity underlies the NOR PUN being series PMOS?

\overline{A+B}=\bar A\cdot\bar B

(AND ⇒ series).

Connections

CMOS Inverter — the 1-input base case of this PUN/PDN principle.
De Morgan's Theorem — the algebra that guarantees PUN/PDN duality.
MOSFET as a Switch — why NMOS pass strong 0, PMOS strong 1.
Static Power and Short-Circuit Current — what the complementary structure prevents.
Logical Effort — quantifies the NAND vs NOR sizing penalty.
Complex Gates (AOI/OAI) — generalizes series/parallel to arbitrary functions.

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

CMOS gate ka fundamental idea simple hai: har gate ke do parts hote hain — upar pull-up network (PUN) jo sirf PMOS se banta hai, aur neeche pull-down network (PDN) jo sirf NMOS se banta hai. NMOS tab ON hota hai jab gate HIGH ho aur woh clean 0 pass karta hai, isliye woh neeche (pull-down) rakha jata hai. PMOS tab ON hota hai jab gate LOW ho aur clean 1 pass karta hai, isliye woh upar (pull-up). Design ka rule ye hai ki PUN aur PDN ek dusre ke dual hone chahiye — taaki har input ke liye exactly ek network conduct kare: output kabhi float na ho aur $V_{DD}$ –GND short kabhi na ho.

Yaad rakhne ka trick: series NMOS = AND, parallel NMOS = OR. NAND banana hai ( $Y=\overline{A\cdot B}$ ) — output 0 tabhi jab dono input 1, yaani AND, yaani do NMOS series mein. Iska dual — PMOS parallel upar. NOR ( $Y=\overline{A+B}$ ) mein ulta: NMOS parallel neeche, PMOS series upar. Bas De Morgan ( $\overline{AB}=\bar A+\bar B$ ) silicon mein apply ho raha hai.

Practical baat: electrons holes se ~2-3 guna fast hote hain, isliye PMOS naturally slow hote hain. Series transistors aur bhi slow hote hain (resistance add). NAND mein PMOS parallel hote hain (achha), par NOR mein PMOS series hote hain (bura) — unhe bahut wide banana padta hai. Isiliye industry mein NAND preferred hota hai — chhota aur fast. Exam aur interview dono mein ye "NAND vs NOR kaun better" wala point pucha jata hai, toh yahi mobility + series-PMOS wali reasoning bolna.

WHY does CMOS work this way?

HOW to build the NAND gate

HOW to build the NOR gate

Sizing: WHY NAND is preferred over NOR

Active Recall

Connections

Concept Map

Hinglish (regional understanding)

Go deeper — visual, from zero

Test yourself — CMOS Circuit Design

Connections