CMOS NAND and NOR gate design: Visual walkthrough — Hardware deep dive

This page re-derives the parent result the CMOS NAND gate purely visually. If a word here is new, we build it before we use it.

Step 1 — What a switch is, and the two kinds we have

WHAT. A switch is a thing on a wire that is either closed (current flows, like a bridge you can walk over) or open (current blocked, like a raised drawbridge). We have two flavours of switch, called NMOS and PMOS transistors. Each has a control wire called the gate. We feed the gate a signal that is either HIGH ( $1$ ) or LOW ( $0$ ).

WHY two kinds. They react to their gate oppositely, and we will need both to cover all cases without ever leaving the output wire dangling. (See MOSFET as a Switch for the physics of why they behave this way.)

PICTURE. Look at the figure. On the left the NMOS: its little bubble-free gate means "close me when the gate is HIGH." On the right the PMOS: the small circle on its gate means "close me when the gate is LOW." The circle is the visual cue for "inverted — flips what closes me."

Step 2 — The output wire, and the rule it must never break

WHAT. We have one output wire, call it $Y$ . Above it sits the power rail $V_{D D}$ (a permanent source of logic $1$ ). Below it sits $GN D$ (a permanent source of logic $0$ ). $Y$ becomes whatever it gets connected to.

WHY. There are exactly two things we must forbid:

Float — $Y$ connected to neither rail. It then holds random leftover charge = garbage.
Short — $Y$ connected to both rails at once. Current pours straight from $V_{D D}$ to $GN D$ , wasting power and giving no clean logic value (see Static Power and Short-Circuit Current).

So the iron rule is: for every input combination, connect $Y$ to exactly one rail.

PICTURE. The wire $Y$ in the middle. A green arrow (allowed) links it to one rail; a red crossed arrow shows the two forbidden states. We will design a top switch-network and a bottom switch-network so that exactly one is closed at any time.

Step 3 — What we actually want the gate to do

WHAT. A NAND of two inputs $A$ and $B$ outputs: $Y = \overline{A \cdot B}$

Read this left to right: $A \cdot B$ is " $A$ AND $B$ " — it is $1$ only when both are $1$ . The bar on top means NOT — flip the result. So $Y$ is $0$ only in the single case where both inputs are $1$ , and $1$ everywhere else.

WHY this shape. Every CMOS gate is naturally inverting — the transistors that pull toward $GN D$ turn ON when their gate is HIGH, so a HIGH input tends to lower the output. So the "N" (NOT) at the front is free; NAND is one of the cheapest useful things silicon can build.

PICTURE. The truth table drawn as four coloured cells — three light (output $1$ ) and one dark (output $0$ ), so you can see that NAND is "mostly 1, with a single 0 in the corner."

Step 4 — Building the pull-DOWN network (when does $Y$ go to 0?)

WHAT. $Y = 0$ must happen only when $A = 1$ AND $B = 1$ . So the PDN must conduct only when both NMOS are closed.

WHY series. Think of a chain of two bridges. To cross from $Y$ down to $GN D$ you must cross both. If either bridge is up, you can't get across. "Both must be closed to complete the path" is exactly the word AND. Two switches where the current must survive the whole chain are said to be in series.

$path conducts = (A ON) \cdot (B ON) = A \cdot B$

Each factor is one switch; the dot ( $\cdot$ ) glues them into a single unbroken road — that dot is the seriesness.

PICTURE. Two NMOS stacked vertically between $Y$ and $GN D$ : gate of the top one wired to $A$ , gate of the bottom to $B$ . Current can drain only through the full stack.

Step 5 — Building the pull-UP network as the mirror (De Morgan in silicon)

WHAT. The PUN must conduct in exactly the rows where the PDN does not — so that the "exactly one" rule of Step 2 holds. The PDN conducts when $A \cdot B = 1$ ; therefore the PUN must conduct when $\overline{A \cdot B} = 1$ . Now use De Morgan's Theorem: $\overline{A \cdot B} = \overset{ˉ}{A} + \overset{ˉ}{B}$

Term by term: the bar over each letter flips it ( $\overset{ˉ}{A}$ = " $A$ is $0$ "); the $+$ means OR. So the PUN conducts when " $A$ is $0$ OR $B$ is $0$ ."

WHY parallel PMOS. A PMOS closes when its gate is LOW, i.e. when its input is $0$ — that matches $\overset{ˉ}{A}$ and $\overset{ˉ}{B}$ perfectly. And OR means "either path is enough," which is two switches side-by-side = in parallel. So: two PMOS in parallel between $V_{D D}$ and $Y$ .

THE RECIPE (the duality rule): to turn any PDN into its PUN, swap series ↔ parallel and NMOS ↔ PMOS. That single swap is De Morgan drawn as wires.

PICTURE. Two PMOS side-by-side (parallel) up top; the series NMOS pair down below. Notice the mirror: series below became parallel above.

Step 6 — Walk EVERY input row (no case left uncovered)

We now check all four rows and confirm exactly-one-conducts each time.

Row $A = 0, B = 0$ . Both NMOS open (gates LOW) ⇒ PDN off. Both PMOS closed (gates LOW) ⇒ PUN on ⇒ $Y = 1$ . ✓ ( $\overline{0 \cdot 0} = 1$ .)

Row $A = 0, B = 1$ . NMOS chain broken ( $A$ -NMOS open) ⇒ PDN off. In the PUN, the $A$ -PMOS is closed (its gate is $0$ ); parallel means one is enough ⇒ PUN on ⇒ $Y = 1$ . ✓

Row $A = 1, B = 0$ . NMOS chain broken ( $B$ -NMOS open) ⇒ PDN off. The $B$ -PMOS is closed (gate $0$ ) ⇒ PUN on ⇒ $Y = 1$ . ✓

Row $A = 1, B = 1$ . Both NMOS closed ⇒ full chain ⇒ PDN on ⇒ $Y = 0$ . Both PMOS open (gates HIGH) ⇒ PUN off. ✓ ( $\overline{1 \cdot 1} = 0$ .)

PICTURE. Four mini-schematics side by side, closed switches drawn solid/mint, open switches faded, with the live current path highlighted in coral. In every panel exactly one path is alive.

Step 7 — The degenerate case: tie the two inputs together

WHAT. Set $A = B$ (feed the same wire to both). Then $Y = \overline{A \cdot A} = \overline{A}$ — the gate collapses into a plain inverter.

WHY show this. It proves the CMOS Inverter is just the one-transistor-per-net baby of this whole scheme: series-of-one is one NMOS, parallel-of-one is one PMOS. Nothing special — the same PUN/PDN duality, with $n = 1$ .

PICTURE. The NAND with both gates wired to a single input $A$ ; the redundant switches greyed, leaving a lone NMOS pull-down and a lone PMOS pull-up — the inverter.

Recall

Tying inputs of a 2-NAND together gives which gate? ::: An inverter, $Y = \overset{ˉ}{A}$ .

Step 8 — Why the PMOS ended up parallel is lucky (sizing)

WHAT. Series switches have their resistances add (longer road = more drag), so a series stack is slow. To fix a slow stack of $n$ transistors you widen each by $n \times$ .

WHY it matters here. PMOS are intrinsically slower than NMOS (holes drift slower than electrons, $μ_{n} \approx k μ_{p}$ with $k \approx 2 - 3$ ). In NAND the slow PMOS are parallel — no widening penalty — while only the fast NMOS are in series. That is exactly why NAND is the preferred building block over NOR (whose PMOS are series and must be bloated to $\sim 2 k$ ). Logical Effort quantifies this.

PICTURE. Two resistor-chains: series (resistances stacked, tall/slow) vs parallel (resistances side by side, short/fast), with the NAND's PMOS pictured on the fast side.

The one-picture summary

Everything on one canvas: target $\overline{A \cdot B}$ → PDN is series NMOS (AND) → De Morgan swap → PUN is parallel PMOS (OR of complements) → exactly one net conducts per row → $Y$ never floats, never shorts.

Recall Feynman retelling in plain words

We had one output wire and a strict rule: always plug it into exactly one of two batteries — the "1" battery on top or the "0" battery on the bottom, never both, never neither. We wanted the wire to read "0" only when both switches $A$ and $B$ are flipped on. So on the bottom we put two switches in a single line: you only reach the "0" battery if you get past both — that's the AND. Then, to obey the rule, the top must plug in on every other occasion. De Morgan told us "not (both on)" is the same as " $A$ off or $B$ off," so up top we used two of the opposite switches side by side — either one being off is enough to grab the "1" battery. We walked all four cases and confirmed exactly one battery is ever connected. Tie the two inputs together and the gate shrinks into a plain inverter. And by happy accident the slow switches (PMOS) landed side-by-side where slowness doesn't hurt — which is why engineers reach for NAND first.

Connections

CMOS Inverter — the $n = 1$ degenerate case built in Step 7.
De Morgan's Theorem — the algebra behind the series↔parallel swap (Step 5).
MOSFET as a Switch — why NMOS/PMOS close on HIGH/LOW (Step 1).
Static Power and Short-Circuit Current — the float/short we forbid (Step 2).
Logical Effort — quantifies the sizing story (Step 8).
Complex Gates (AOI/OAI) — generalizes the series/parallel recipe.