Intuition The one core ideaA CMOS gate is just two teams of switches fighting over one wire : a top team that can only pull the wire UP to "full" and a bottom team that can only pull it DOWN to "empty." The whole subject is the rule that makes exactly one team win for every possible input — so the wire is never left floating and the two teams never both pull at once (which would burn power).
Before you can read the parent note on NAND and NOR gates, you need to own every symbol it throws at you. This page builds each one from nothing — plain words first, then a picture, then why the topic can't live without it. Read top to bottom; each idea leans on the one above it.
V D D GN D
V D D top rail — the highest voltage the chip supplies (say 1.8 GN D bottom rail — zero volts, the drain at the bottom.A wire sitting near V D D call logic 1 . A wire near GN D logic 0 .
The subscript "D D between them.
"Logic 1" and "logic 0" are not separate physical things — they are just which rail a wire is close to . High voltage = 1, low voltage = 0. Everything in this topic is about steering a wire to one rail or the other .
Why the topic needs this: a logic gate's whole job is to decide, for a given output wire Y
Definition The overbar (complement)x x bar " or "not x") is the opposite of x 0 = 1 1 = 0 x x
The parent note writes A ˉ f ˉ A ⋅ B whole expression means: work out the expression first, then flip the final answer.
Why the topic needs this: CMOS gates are physically inverting — the structure naturally produces something
Definition The dot and the plus
A ⋅ B A B A AND B " — true (=1) only when both are 1.A + B A OR B " — true (=1) when at least one is 1.
These are logic operations, not ordinary arithmetic. In particular 1 + 1 = 1
A B A ⋅ B A + B
0
0
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1 1
Why the topic needs this: the very functions we build are A ⋅ B A + B
This is the picture the entire topic rides on. A switch is a gap in a wire that is either CLOSED (current flows, call it ON) or OPEN (no current, OFF).
Definition Series and parallel
Series = switches in a single line, one after another. Current gets through only if every switch is ON . That is an AND of the switches.Parallel = switches side-by-side on separate branches. Current gets through if any one branch is ON. That is an OR of the switches.
Intuition Why series = AND and parallel = ORSeries is a chain : the weakest link breaks it, so you need them all closed — that's "A AND B." Parallel is a choice of doors : opening any single door lets you through — that's "A OR B."
Common mistake "Series feels likeeither one"
Why it feels right: two things "in a row" sounds like "one or the other." Fix: in a line , the current must survive the whole chain. If any switch is open, nothing flows. So series demands all ON → AND. Whenever you're tempted, picture a broken link snapping the chain.
Why the topic needs this: this single mapping — series = AND, parallel = OR — is how logic (algebra) becomes wiring (silicon). It is the hinge of the whole chapter.
A transistor is a switch whose "finger" is a voltage on a control terminal called the gate . There are two flavours, and their difference is the second pillar of the topic.
NMOS : ON (conducts) when its gate is HIGH (1) . It delivers a clean 0 to the output.PMOS : ON when its gate is LOW (0) . It delivers a clean 1 to the output. (The little bubble on its gate symbol is a reminder: "activated by 0.")
They are opposites: at any single gate voltage, exactly one flavour is ON.
Intuition Why "pass a strong 0 / strong 1"?Each type is good at one job . NMOS can drag a wire firmly down to GN D V D D V D D 0 (the pull-DOWN team) and PMOS where you want to reach 1 (the pull-UP team). Placement follows the clean value, not the transistor's "preference." (See MOSFET as a Switch .)
Why the topic needs this: PDN and PUN are literally made of these two switch types. Get the ON-conditions right and the rest of CMOS falls out mechanically.
Definition The three names
Y output wire , the single wire the gate produces.PDN (Pull-Down Network) — the team of NMOS switches between Y GN D Y 0 .PUN (Pull-Up Network) — the team of PMOS switches between V D D Y Y 1 .
Intuition The exactly-one rule
If both teams conducted, V D D GN D Y short-circuit , wasting power for nothing.
If neither conducted, Y floats and holds random garbage.
The fix: design PUN and PDN as logical opposites (duals) so that for every input, exactly one is ON. That's the whole game. (See Static Power and Short-Circuit Current .)
Why the topic needs this: NAND and NOR are just two specific PUN/PDN pairs. Once you know "exactly one conducts," verifying a gate is just checking each input row.
does for us
The PDN pulls Y f Y opposite condition, f f series↔parallel and swap NMOS↔PMOS . That is why the PUN is a mirror of the PDN. (Full algebra: De Morgan's Theorem .)
Worked check of the flip you'll use for NAND:
A ⋅ B = A + B
Why the topic needs this: De Morgan is the proof that duality works. Without it, "swap series and parallel" would just be a lucky trick.
The last cluster of symbols appears only in the sizing discussion (why NAND beats NOR).
Definition Width and mobility
W width of a transistor. Wider = more current = faster (like a wider pipe).μ n electrons move (NMOS carriers). μ p holes move (PMOS carriers).Electrons are faster: μ n ≈ 2 – 3 μ p k = μ n / μ p
R resistance , "how much a switch fights the current." Low R add up (R series = ∑ R i
Intuition The punchline in advanceBecause PMOS are the slow ones, you want them parallel (parallel doesn't stack resistance), not in a slow series chain. NAND puts PMOS in parallel — good. NOR puts them in series — you must fatten them (bigger W Logical Effort formalises it.
Why the topic needs this: these symbols turn "NAND vs NOR" from a hand-wave into a number.
Voltage rails VDD and GND
Switch series and parallel
Sizing W mobility resistance
This feeds directly into the parent topic , whose 1-input base case is the CMOS Inverter and whose general form is Complex Gates (AOI/OAI) .
What does the overbar x Flips it: 0 = 1 1 = 0
When is A ⋅ B Only when both A B
When is A + B When at least one of A B
Series switches implement which logic operation, and why? AND — current must survive the whole chain, so all must be ON.
Parallel switches implement which logic operation? OR — any one closed branch lets current through.
When is an NMOS ON, and which clean value does it pass? ON when gate is HIGH (1); passes a strong 0.
When is a PMOS ON, and which clean value does it pass? ON when gate is LOW (0); passes a strong 1.
Which network holds NMOS and which holds PMOS? PDN = NMOS (pulls Y Y
What two bad things happen if the exactly-one-conducts rule breaks? Both ON → short-circuit (V D D GN D Y
State one De Morgan law in words. "Break the bar, flip the operator": A ⋅ B = A + B
Why are PMOS the ones we worry about sizing? Holes are slower (μ n ≈ 2 – 3 μ p