CMOS NAND and NOR gate design: Exercises — Hardware deep dive

Before we start, one shared picture that every problem leans on:

Definition Symbols used on this page (open if unsure)

$V_{D D}$ ::: the supply rail = logic $1$ voltage (the "top" wire).
$GN D$ ::: ground = logic $0$ voltage (the "bottom" wire).
PUN ::: Pull-Up Network — PMOS transistors between $V_{D D}$ and output $Y$ .
PDN ::: Pull-Down Network — NMOS transistors between $Y$ and $GN D$ .
$μ_{n}, μ_{p}$ ::: how fast electrons / holes move. $k = μ_{n} / μ_{p}$ is the mobility ratio (typically $2$ – $3$ ).
$W$ ::: transistor width. Wider = lower resistance = more current = faster.
"unit" transistor ::: a reference-size device. NMOS unit width $= 1$ ; a matched-drive inverter uses PMOS width $= k$ .

L1 — Recognition

Problem 1.1

A student points at a network of two transistors in series connecting the output node $Y$ to $GN D$ . What logic operation does this implement, and what transistor type must these be?

Recall Solution 1.1

A path from $Y$ to $GN D$ is the pull-down path, so the devices are NMOS. Series means current must survive the whole chain — both switches must be ON. "Both ON" is the AND operation. So: series NMOS = AND, and pulling $Y$ down to $0$ when $A \cdot B = 1$ . This is the PDN of a NAND gate.

Problem 1.2

Fill in: PMOS conducts (turns ON) when its gate is ______, and it passes a strong logic . Therefore it belongs in the pull- network.

Recall Solution 1.2

PMOS conducts when its gate is LOW ( $0$ ). It passes a strong $1$ . So it belongs in the pull-UP network (pulling $Y$ toward $V_{D D} = 1$ ).

Problem 1.3

Name the two De Morgan identities and match each to whether it produces series or parallel PMOS in the PUN.

Recall Solution 1.3

$\overline{A \cdot B} = \overset{ˉ}{A} + \overset{ˉ}{B}$ → an OR of complements → parallel PMOS (this is NAND's PUN).
$\overline{A + B} = \overset{ˉ}{A} \cdot \overset{ˉ}{B}$ → an AND of complements → series PMOS (this is NOR's PUN).

L2 — Application

Problem 2.1

Build the transistor topology of a 2-input NAND ( $Y = \overline{A \cdot B}$ ). List PDN and PUN, then verify the input $A = 0, B = 1$ .

Recall Solution 2.1

PDN: $Y = 0$ only when $A \cdot B = 1$ → AND → 2 NMOS in series ( $Y$ to $GN D$ ).
PUN (dual): swap series→parallel, NMOS→PMOS → 2 PMOS in parallel ( $V_{D D}$ to $Y$ ).
Verify $A = 0, B = 1$ : PDN needs both NMOS ON; the $A$ -NMOS has gate $= 0$ → OFF → PDN broken. PUN: the $A$ -PMOS has gate $= 0$ → ON → pulls $Y = 1$ . And $\overline{0 \cdot 1} = \overline{0} = 1$ . ✓

Problem 2.2

Build the 2-input NOR ( $Y = \overline{A + B}$ ). Give PDN and PUN, then verify $A = 1, B = 1$ .

Recall Solution 2.2

PDN: $Y = 0$ when $A + B = 1$ → OR → 2 NMOS in parallel.
PUN: $\overline{A + B} = \overset{ˉ}{A} \cdot \overset{ˉ}{B}$ → AND of complements → 2 PMOS in series.
Verify $A = 1, B = 1$ : PDN parallel — both NMOS ON → pulls $Y = 0$ . PUN series — each PMOS gate $= 1$ → OFF → no pull-up. $\overline{1 + 1} = \overline{1} = 0$ . ✓

Problem 2.3

For a matched-drive design with mobility ratio $k = μ_{n} / μ_{p} = 2$ , give the transistor widths for the 2-input NAND and the 2-input NOR (NMOS unit width $= 1$ , inverter PMOS width $= k$ ). Which is bigger, and why?

Recall Solution 2.3

Rule: $m$ transistors in series must each be $m \times$ wider to keep the same series resistance; parallel devices are unaffected.

NAND: NMOS in series ( $m = 2$ ) → width $2$ ; PMOS parallel → width $k = 2$ . Widths: N=2, P=2.
NOR: NMOS parallel → width $1$ ; PMOS in series ( $m = 2$ ) → width $2 k = 4$ . Widths: N=1, P=4. NOR is bigger because its slow PMOS are in series and must be widened to $2 k = 4$ . Total transistor width: NAND $= 2 + 2 = 4$ per input path pair; NOR $= 1 + 4 = 5$ . NAND wins.

L3 — Analysis

Problem 3.1

A 2-input CMOS gate has PDN = 2 NMOS in parallel and PUN = 2 PMOS in series. Without being told the name, derive the Boolean function $Y (A, B)$ and identify the gate.

Recall Solution 3.1

PDN parallel NMOS → conducts (pulls $Y = 0$ ) when $A$ OR $B$ is HIGH, i.e. when $A + B = 1$ .
$Y$ is $0$ exactly when $A + B = 1$ , so $Y = \overline{A + B}$ .
PUN series PMOS confirms it: conducts (pulls $Y = 1$ ) only when both gates LOW, i.e. $\overset{ˉ}{A} \cdot \overset{ˉ}{B} = 1$ , and $\overline{A + B} = \overset{ˉ}{A} \cdot \overset{ˉ}{B}$ ✓ (De Morgan).
This is a 2-input NOR.

Problem 3.2

Consider the NAND gate at input $A = 1, B = 0$ . Trace every transistor's state, confirm exactly one network conducts, and confirm there is no $V_{D D}$ -to- $GN D$ short and no floating output.

Recall Solution 3.2

NAND: PDN = series NMOS ( $N_{A}, N_{B}$ ); PUN = parallel PMOS ( $P_{A}, P_{B}$ ). Gates driven by $A, B$ .

$N_{A}$ : gate $= A = 1$ → ON. $N_{B}$ : gate $= B = 0$ → OFF. Series pair → broken (one OFF kills the chain) → PDN OFF.
$P_{A}$ : gate $= A = 1$ → OFF. $P_{B}$ : gate $= B = 0$ → ON. Parallel → one ON path is enough → PUN ON.
Exactly one net (PUN) conducts → $Y = 1 = \overline{1 \cdot 0}$ ✓.
No short: PDN is OFF while PUN is ON, so no continuous $V_{D D} \to GN D$ path.
No float: PUN actively drives $Y$ to $V_{D D}$ .

Problem 3.3

"Broken-dual" bug. An engineer wires a gate with PDN = 2 NMOS in series (a correct NAND PDN) but by mistake also makes the PUN = 2 PMOS in series. For input $A = 0, B = 0$ , what happens to $Y$ , and why is this a hardware failure?

Recall Solution 3.3

Correct NAND wants PUN = parallel PMOS. Here PUN is series (bug).
At $A = 0, B = 0$ : PDN series NMOS — both gates $0$ → both OFF → PDN OFF. PUN series PMOS — both gates $0$ → both ON → PUN conducts, so $Y = 1$ . This particular row happens to look right.
But test $A = 0, B = 1$ : PDN — $N_{B}$ needs gate $1$ ON, $N_{A}$ gate $0$ OFF → PDN OFF (fine). PUN series — $P_{A}$ gate $0$ ON, $P_{B}$ gate $1$ OFF → PUN OFF. Now neither network conducts → $Y$ floats (holds garbage / high-impedance). ✗
Failure mode: the networks are no longer duals, so the "exactly one conducts" guarantee is broken → floating output on some inputs. The correct NAND is $\overline{A \cdot B}$ ; a series-PUN gate is not the complement of a series-PDN gate.

L4 — Synthesis

Problem 4.1

Design a CMOS gate for $Y = \overline{A \cdot B + C}$ (an AOI — AND-OR-Invert). Give the PDN and the dual PUN, and describe each transistor's connection.

Recall Solution 4.1

Read the un-inverted expression $f = A \cdot B + C$ to build the PDN (PDN conducts when $f = 1$ ):

$A \cdot B$ → series NMOS pair $(N_{A}, N_{B})$ .
$+ C$ → that pair is in parallel with a single NMOS $N_{C}$ .
PDN: $(N_{A}$ series $N_{B})$ in parallel with $N_{C}$ , between $Y$ and $GN D$ .

PUN = full dual (swap series↔parallel, NMOS→PMOS):

The AND ( $A \cdot B$ ) becomes parallel; the OR ( $+ C$ ) becomes series.
PUN: $(P_{A}$ parallel $P_{B})$ in series with $P_{C}$ , between $V_{D D}$ and $Y$ .
Check with De Morgan: $Y = \overline{A B + C} = \overline{A B} \cdot \overline{C} = (\overset{ˉ}{A} + \overset{ˉ}{B}) \cdot \overset{ˉ}{C}$ → an OR ( $\overset{ˉ}{A} + \overset{ˉ}{B}$ , parallel) ANDed with $\overset{ˉ}{C}$ (series) ✓.

Problem 4.2

For the AOI gate of 4.1, size the transistors for equal drive (mobility ratio $k$ , NMOS unit $= 1$ , inverter PMOS $= k$ ). Find the worst-case NMOS series width and the worst-case PMOS series width.

Recall Solution 4.2

PDN worst-case series path: the longest chain that must sink current is $N_{A}$ – $N_{B}$ (2 in series). Each → width $2$ . ( $N_{C}$ alone → width $1$ .)
PUN worst-case series path: $P_{C}$ is in series with the parallel pair. Trace the longest PMOS chain that must source current: through $P_{C}$ then either $P_{A}$ or $P_{B}$ — that's 2 PMOS in series. Each PMOS in that series path → width $2 k$ . (If the pair were counted as one effective device, the series depth from $V_{D D}$ to $Y$ is 2.)
So: series NMOS width $= 2$ ; series PMOS width $= 2 k$ . As always, the PMOS series stack is the area/speed cost.

Problem 4.3

Build $Y = \overline{(A + B) \cdot C}$ (an OAI — OR-AND-Invert). Give PDN and PUN.

Recall Solution 4.3

Build PDN from $f = (A + B) \cdot C$ :

$A + B$ → parallel NMOS $(N_{A} ∥ N_{B})$ .
$\cdot C$ → put that parallel block in series with $N_{C}$ .
PDN: $(N_{A} ∥ N_{B})$ in series with $N_{C}$ , from $Y$ to $GN D$ .

PUN = dual: parallel→series, series→parallel, NMOS→PMOS:

$A + B$ (parallel) → series PMOS $(P_{A}$ series $P_{B})$ .
in series with $N_{C}$ → becomes parallel with $P_{C}$ .
PUN: $(P_{A}$ series $P_{B})$ in parallel with $P_{C}$ , from $V_{D D}$ to $Y$ .
De Morgan check: $\overline{(A + B) C} = \overline{A + B} + \overset{ˉ}{C} = (\overset{ˉ}{A} \overset{ˉ}{B}) + \overset{ˉ}{C}$ → an AND ( $\overset{ˉ}{A} \overset{ˉ}{B}$ , series) ORed with $\overset{ˉ}{C}$ (parallel) ✓.

L5 — Mastery

Problem 5.1

You must drive a large load and the vendor library offers only NAND and NOR cells with the sizings from Problem 2.3 ( $k = 2$ : NAND N=2/P=2, NOR N=1/P=4). You need a 2-input NOR function. Argue whether it is cheaper (in total transistor width) to (a) use the NOR cell directly, or (b) synthesize NOR from a NAND cell plus inverters using De Morgan. Assume an inverter costs N=1, P= $k$ =2 (width $1 + 2 = 3$ ).

Recall Solution 5.1

(a) NOR cell direct: total width $= 1 + 4 = 5$ .
(b) De Morgan route: $\overline{A + B} = \overset{ˉ}{A} \cdot \overset{ˉ}{B}$ . So NOR $=$ invert $A$ , invert $B$ , then... a NAND of the inverted inputs gives $\overline{\overset{ˉ}{A} \overset{ˉ}{B}} = A + B$ (an OR, wrong), then invert → 2 inverters + NAND + inverter. Simplest correct build: $\overline{A + B}$ via NAND needs $\overline{A + B} = \overline{\overline{\overset{ˉ}{A} \overset{ˉ}{B}}}$ ... this balloons. Even the minimal working chain is 2 input-inverters + NAND ( $= 4$ ) + output inverter, i.e. $2 (3) + 4 + 3 = 13$ width.
Conclusion: the direct NOR cell (width $5$ ) is far cheaper than synthesizing it ( $\approx 13$ ). The De Morgan trick is for logic manipulation, not for saving transistors when the target cell already exists. Direct NOR wins: $5 < 13$ .

Problem 5.2

Full mastery check. A gate is specified by the truth table below. Recover $Y (A, B)$ , decide NAND or NOR, give the transistor topology, and confirm "exactly one network conducts" for the row $A = 0, B = 1$ .

A	B	Y
0	0	1
0	1	1
1	0	1
1	1	0

Recall Solution 5.2

$Y = 0$ only at $A = 1, B = 1$ , i.e. when $A \cdot B = 1$ . So $Y = \overline{A \cdot B}$ → NAND.
Topology: PDN = 2 NMOS in series; PUN = 2 PMOS in parallel.
Row $A = 0, B = 1$ : PDN series — $N_{A}$ gate $0$ OFF, $N_{B}$ gate $1$ ON → chain broken → PDN OFF. PUN parallel — $P_{A}$ gate $0$ ON, $P_{B}$ gate $1$ OFF → one ON path → PUN ON. Exactly one conducts (PUN) → $Y = 1$ ✓, matches the table.

Problem 5.3

Timing insight. For the NAND ( $k = 2$ , N=2/P=2) versus NOR ( $k = 2$ , N=1/P=4), the worst-case pull-up delay scales with the series-PMOS resistance. Model each PMOS unit-resistance as $R_{p}$ (for a unit-width device) so a width- $w$ device has resistance $R_{p} / w$ . Compute the worst-case pull-up resistance of each gate and state which is slower to pull HIGH.

Recall Solution 5.3

Resistance of a width- $w$ PMOS $= R_{p} / w$ . Series resistances add.

NAND pull-up: PMOS are parallel, each width $2$ . Worst case only one path is ON (e.g. $A = 1, B = 0$ → only $P_{B}$ on): $R_{u p} = R_{p} /2$ .
NOR pull-up: PMOS are series, each width $4$ . Both in series: $R_{u p} = R_{p} /4 + R_{p} /4 = R_{p} /2$ .
By design both hit $R_{p} /2$ — that's exactly why NOR PMOS were widened to $4$ (to compensate the series stack). The catch: NOR paid double the area ( $4$ vs $2$ ) to reach the same speed. So NOR is not slower here, but it is bigger and more capacitive, which is the real penalty. NAND is preferred: same drive, less width.

Connections

MOSFET as a Switch — the ON/OFF rules every solution above relies on.
De Morgan's Theorem — the engine behind every PUN-from-PDN dual.
Complex Gates (AOI/OAI) — L4 problems 4.1–4.3 are its base cases.
Logical Effort — formalizes the width/delay trade-offs of L5.
Static Power and Short-Circuit Current — what problem 3.3's broken dual would violate.
CMOS Inverter — the 1-input cell used for sizing baselines.
CMOS NAND and NOR gate design — parent topic.