CMOS NAND and NOR gate design: Question bank — Hardware deep dive

Read each prompt, commit to an answer out loud, then reveal. If your reason differs from the reveal even when the verdict matches, you got lucky, not right.

First: the vocabulary these traps assume

Before any trap, pin down every symbol so no reveal below uses an undefined term.

Look at the picture: the PUN sits on top pulling $Y$ toward $V_{D D}$ , the PDN sits below pulling $Y$ toward $GN D$ , and $f$ / $\overset{ˉ}{f}$ label which side is allowed to win.

Here is the schematic that every NAND / NOR trap below refers to — study it once, then the reveals will make sense visually, not just verbally.

True or false — justify

A CMOS gate can, for some input, have both PUN (Pull-Up Network) and PDN (Pull-Down Network) OFF at once.

False — PUN and PDN are logical duals, so for every input exactly one conducts; if both were off, output node

Y

would float and hold stale charge.

A CMOS gate can, for some input, have both PUN and PDN ON at once.

False (in steady state) — duality guarantees the two conduction conditions

f

(pull LOW) and

\overset{ˉ}{f}

(pull HIGH) are complementary, so they never overlap; simultaneous ON would short

V_{D D}

GN D

Series NMOS transistors implement a logical OR.

False — current must survive the whole chain, so all switches must be ON: series = AND (see the series panel). OR needs two independent parallel branches.

The PUN of a NAND gate is two PMOS in parallel.

True —

\overline{A \cdot B} = \overset{ˉ}{A} + \overset{ˉ}{B}

is an OR of complements, and OR ⇒ parallel; with PMOS the "gate LOW" condition supplies the complement automatically.

In a NOR gate the two PMOS sit in series.

True —

\overline{A + B} = \overset{ˉ}{A} \cdot \overset{ˉ}{B}

is an AND of complements, AND ⇒ series, which is exactly why NOR's PMOS stack is slow and must be widened.

Making the PUN a mirror of the PDN means literally copying the same series/parallel wiring.

False — you must swap series↔parallel (and NMOS↔PMOS). Copying the topology would break duality and give a non-inverting, possibly shorting network.

An NMOS transistor placed in the pull-up network would still work fine electrically.

False in practice — NMOS passes a weak 1 (it degrades a high by a threshold drop

V_{D D} - V_{t h}

), so the output "1" would be dim and slow; that's why PMOS, which pass a strong 1, occupy the PUN. See MOSFET as a Switch for the threshold-drop picture.

For a 2-input NAND, the NMOS must be sized wider than in an inverter but the PMOS need not be.

True — the two NMOS are in series (resistances add), so each is doubled to

W_{n} = 2 W_{u ni t}

; the PMOS are in parallel, unaffected, staying at the balanced-inverter width

k

Spot the error

"PMOS go in the pull-down network because PMOS like logic 1 and pull-down handles the output."

The error conflates a transistor's pass strength with the network's pull direction. Pull-down pulls toward

GN D = 0

; NMOS pass a strong 0, so NMOS ⇒ pull-down. PMOS pass a strong 1 ⇒ pull-up.

"Since NAND is

\overline{A \cdot B}

, its PDN is two NMOS in parallel (one per input)."

Wrong topology.

Y = 0

only when

A \cdot B = 1

, i.e. both high — that requires series NMOS (an AND path). Parallel would pull low if either were high, giving a NOR.

"NOR is built with parallel PMOS on top because parallel is faster."

The De Morgan algebra, not speed, fixes the topology:

\overline{A + B} = \overset{ˉ}{A} \cdot \overset{ˉ}{B}

forces series PMOS. The slowness of that series stack is precisely the penalty, not something you can wire away.

"If exactly one network conducts, static power is zero, so CMOS never dissipates power."

It eliminates steady-state static current, but not short-circuit current during switching (a brief instant both are partly on) nor leakage — see Static Power and Short-Circuit Current.

"A 3-input NAND just adds another PMOS in series to the pull-up."

Backwards — 3-input NAND is

\overline{A B C} = \overset{ˉ}{A} + \overset{ˉ}{B} + \overset{ˉ}{C}

, an OR ⇒ the extra PMOS goes in parallel. The three NMOS are the ones that stack in series in the PDN.

"Widening the series PMOS in NOR fixes speed without any cost."

Widening a PMOS by factor

m

cuts its resistance to

R / m

but raises its gate capacitance to

m C

. The previous stage now drives a bigger

C

, so its delay

\propto R_{p r e v} (m C)

grows — the speed you buy in this gate is partly paid back as slower rise at the driver. The trade never fully disappears; see Logical Effort.

"De Morgan says

\overline{A \cdot B} = \overset{ˉ}{A} \cdot \overset{ˉ}{B}

, which is why NAND's PUN is series."

The identity is misquoted. Correct:

\overline{A \cdot B} = \overset{ˉ}{A} + \overset{ˉ}{B}

(product's complement is a sum), so NAND's PUN is parallel, not series.

Why questions

Why must the PUN and PDN be logical duals rather than any two complementary-looking nets?

Only strict duality (series↔parallel swap of the same variables) guarantees their conduction conditions are exact logical complements

f

and

\overset{ˉ}{f}

— that's what forbids both floating and shorting for all inputs, not just some.

Why is NAND the default gate in standard-cell libraries over NOR?

NAND keeps the slow PMOS in parallel (unstacked, width

k

), so only the fast NMOS stack in series; NOR stacks the slow PMOS in series, forcing large widths (~

2 k

) that cost area and speed.

Why do NMOS pass a strong 0 but a weak 1?

An NMOS conducts well while its gate-to-source voltage stays above

V_{t h}

; passing a 0 keeps the source near ground (large drive), but passing a 1 raises the source until

V_{GS}

drops below

V_{t h}

and it cuts off a threshold below

V_{D D}

. See MOSFET as a Switch.

Why does making series transistors wider recover their speed?

Series resistances add, so an

n

-stack has

\sim n \times

the on-resistance; multiplying each width by

n

cuts each device's resistance by

n

, restoring the single-transistor drive at the cost of area.

Why, quantitatively, does a 2-input NAND set

W_{n} = 2 W_{u ni t}

In the worst pull-down case only the series chain of two NMOS conducts. Two equal resistors in series give

R_{ser i es} = R_{1} + R_{2} = 2 R_{u ni t}

. To match the single-transistor target

R_{u ni t}

, and since

R \propto 1/ W

, we need each width scaled by

2

W_{e a c h} = 2 W_{u ni t}

, giving

R_{ser i es} = 2 \cdot (R_{u ni t} /2) = R_{u ni t}

. ✓

Why does the "series = AND" rule map so cleanly onto De Morgan?

A series NMOS path pulls

Y

low iff all inputs are high (AND ⇒

\overline{A \cdot B}

output), and its dual PUN pulls high iff all complements are high (parallel ⇒

\overset{ˉ}{A} + \overset{ˉ}{B}

) — the two networks are the two sides of De Morgan realised in silicon.

Why can't we just use a single NMOS pull-down and a resistor pull-up (pseudo-NMOS) instead of full CMOS?

When the NMOS conducts, the resistor path stays connected, drawing continuous static current (a shorted

V_{D D} \to GN D

path) — exactly the dissipation the complementary PUN was designed to eliminate.

Edge cases

For NAND with

A = 1, B = 0

, which network conducts and what is

Y

The PUN conducts via the

B

-PMOS (gate

= 0

⇒ ON); the series NMOS is broken at

B

, so PDN is off.

Y = 1

, matching

\overline{1 \cdot 0} = 1

For NAND with

A = 1, B = 1

(both inputs high), which network conducts and what is

Y

Both series NMOS are ON, so the PDN completes a path to

GN D

and pulls

Y

down; both PMOS are off.

Y = 0

— the sole low row of NAND, confirming

\overline{1 \cdot 1} = 0

For NOR with

A = 0, B = 0

(both inputs low), what is the state?

Both PMOS are ON (series path complete) and both NMOS off, so

Y = 1

— the only high-output row of the NOR, matching

\overline{0 + 0} = 1

For NOR with

A = 1, B = 0

, which network conducts and what is

Y

The parallel PDN conducts via the

A

-NMOS (gate

= 1

⇒ ON), pulling

Y

low; the series PMOS stack is broken because the

A

-PMOS (gate

= 1

) is off.

Y = 0

, matching

\overline{1 + 0} = 0

For NOR with

A = 1, B = 1

(both inputs high), which network conducts and what is

Y

Both parallel NMOS are ON (either alone would suffice), so the PDN pulls

Y

low; both series PMOS are off.

Y = 0

, matching

\overline{1 + 1} = 0

What is the degenerate case of a "1-input NAND" and what does it reduce to?

A single NMOS pull-down and single PMOS pull-up — it collapses into the plain CMOS Inverter, the base case of the whole PUN/PDN principle.

What is a 0-input NAND or NOR — does the family even extend that far?

Yes, degenerately. By convention an empty AND

= 1

and an empty OR

= 0

; a NAND inverts its AND and a NOR inverts its OR, so a 0-input NAND is

\overline{1} =

constant 0 and a 0-input NOR is

\overline{0} =

constant 1. In practice such a "gate" is just a hard-wired constant —

Y

tied straight to

GN D

(for the NAND) or to

V_{D D}

(for the NOR) — not a switching cell.

In the NAND row

A = 0, B = 1

, is the unused-looking

A

-PMOS actually doing the work?

Yes — the

A

-PMOS (gate

= 0

) is ON and supplies the pull-up path; the

B

-PMOS is off. Because the PUN is parallel, one ON branch is enough to give

Y = 1

If both inputs of a 2-input NAND are tied together (

A = B

), what gate results?

Series NMOS both switched by the same signal act as one (stronger-resistance) NMOS, and parallel PMOS act as one — the gate becomes an inverter of that shared input,

Y = \overline{A}

During the instant an input transitions, can both networks momentarily conduct?

Yes — while the input passes through the region where NMOS and PMOS are both partially on, a brief short-circuit current flows; this transient (not steady state) is a real dynamic-power contributor, covered in Static Power and Short-Circuit Current.

Connections

Parent: NAND/NOR design — the full build and sizing derivation these traps test.
De Morgan's Theorem — the algebra behind every "series vs parallel" trap here.
MOSFET as a Switch — grounds the strong-0 / weak-1 edge cases.
Static Power and Short-Circuit Current — the "power is zero" and transient-short items.
Logical Effort — quantifies the NAND-vs-NOR sizing "why" questions.
Complex Gates (AOI/OAI) — generalises the series/parallel traps to multi-input functions.