CMOS NAND and NOR gate design: Worked examples — Hardware deep dive

Before anything: two words we will lean on constantly.

We write logic $1$ for the high voltage $V_{D D}$ and $0$ for ground $GN D$ . The output node is $Y$ .

The scenario matrix

Every question this topic can throw lives in one of these cells. Each worked example below is tagged with the cell it covers.

Cell	What it stresses	Example
C1 All-inputs-low ( $A = 0, B = 0$ )	degenerate: nothing HIGH	Ex 1
C2 One-high-one-low ( $A \neq = B$ )	asymmetric — the tricky row	Ex 2
C3 All-inputs-high ( $A = 1, B = 1$ )	degenerate: everything HIGH	Ex 3
C4 Full truth sweep, both gates	every row at once	Ex 4
C5 Safety limit	prove never-short / never-float	Ex 5
C6 Sizing, series vs parallel	limiting resistance behaviour	Ex 6
C7 3-input generalisation	scaling the rule up	Ex 7
C8 Real-world word problem	stopwatch / alarm design	Ex 8
C9 Exam twist — reverse-engineer	given transistors, find $Y$	Ex 9

Example 1 — Cell C1: both inputs LOW

Example 2 — Cell C2: mixed inputs $A = 1, B = 0$

Example 3 — Cell C3: both inputs HIGH (the only 0-output row of NAND)

Example 4 — Cell C4: full truth sweep of BOTH gates

Worked example

Statement. Fill the complete truth table for 2-input NAND and 2-input NOR, and note which network conducts each row.

Forecast: NAND is $1$ except when both are $1$ ; NOR is $1$ only when both are $0$ .

Step 1 — NAND (series N / parallel P). Why this step? Apply the AND-fires-only-when-all-HIGH rule row by row.

$A$	$B$	conducting net	$Y_{NAND}$
0	0	PUN	1
0	1	PUN	1
1	0	PUN	1
1	1	PDN	0

Step 2 — NOR (parallel N / series P). Why this step? OR-fires-when-any-HIGH pulls $Y$ down in three rows.

$A$	$B$	conducting net	$Y_{NOR}$
0	0	PUN	1
0	1	PDN	0
1	0	PDN	0
1	1	PDN	0

Verify: Each $Y_{NAND} = \overline{A \cdot B}$ and $Y_{NOR} = \overline{A + B}$ . In every row exactly one network conducts. ✓

Example 5 — Cell C5: prove the safety limit (never short, never float)

Worked example

Statement. Across all $4$ input rows of the NAND, count how many rows have (a) both networks on — a short $V_{D D} \to GN D$ , or (b) neither on — a float. Show both counts are $0$ .

Forecast: By duality both should be zero — otherwise CMOS would burn power or hold garbage (see Static Power and Short-Circuit Current).

Step 1 — Write PDN and PUN as boolean "on" conditions. Why this step? Turn "conducts" into algebra we can sum. PDN (series N) is on when $A \cdot B = 1$ . PUN (parallel P) is on when $\overset{ˉ}{A} + \overset{ˉ}{B} = 1$ .

Step 2 — Short count = rows where $(A \cdot B) \land (\overset{ˉ}{A} + \overset{ˉ}{B}) = 1$ . Why this step? Short = both on simultaneously. $(A \cdot B) \land (\overset{ˉ}{A} + \overset{ˉ}{B}) = \overline{(A \cdot B)} \land (A \cdot B) = 0$ for all inputs (a thing AND its complement). Short rows = 0. ✓

Step 3 — Float count = rows where neither is on = $\overline{A \cdot B} \land \overline{\overset{ˉ}{A} + \overset{ˉ}{B}}$ . Why this step? Float = both off. $\overline{\overset{ˉ}{A} + \overset{ˉ}{B}} = A \cdot B$ , so this is $\overline{A \cdot B} \land (A \cdot B) = 0$ . Float rows = 0. ✓

Verify: Both counts are $0$ over all $4$ rows. This is De Morgan's Theorem guaranteeing exactly-one-conducts. ✓

Example 6 — Cell C6: sizing at the limit (series doubles, parallel doesn't)

Worked example

Statement. Take $k = μ_{n} / μ_{p} = 2$ so an inverter uses $W_{n} : W_{p} = 1 : 2$ . Size a 2-input NAND and a 2-input NOR to match that inverter's worst-case drive strength. Compute the total transistor width of each.

Forecast: NOR should come out bigger because its PMOS are in series.

Step 1 — Rule: $n$ transistors in series each need $n \times$ width. Why this step? Series resistances add ( $R_{ser i es} = \sum R_{i}$ ); to keep total resistance equal to one unit device, each of the $n$ must be $n \times$ wider so its resistance is $1/ n$ of unit.

Step 2 — NAND. NMOS: 2 in series → each width $2$ , two of them $= 2 + 2 = 4$ . PMOS: 2 in parallel → parallel does not add series resistance, each stays at inverter width $k = 2$ , two of them $= 2 + 2 = 4$ . Total NAND width $= 4 + 4 = 8$ . Why this step? Parallel is unaffected because the worst case (one path) already has one full-width device.

Step 3 — NOR. NMOS: 2 in parallel → each width $1$ , two $= 1 + 1 = 2$ . PMOS: 2 in series → each $2 k = 4$ , two $= 4 + 4 = 8$ . Total NOR width $= 2 + 8 = 10$ .

Verify: NAND total $= 8$ , NOR total $= 10$ . NOR is larger (the series-PMOS $2 k = 4$ each is the culprit), confirming NAND-preferred. See Logical Effort. ✓

Example 7 — Cell C7: generalise to a 3-input NAND

Example 8 — Cell C8: real-world word problem (a two-key launch interlock)

Worked example

Statement. A machine must run only when both the operator key $A$ and the supervisor key $B$ are inserted (each key inserted $= 1$ ). You have one CMOS gate driving an active-LOW "STOP" line: STOP is asserted (line $= 0$ ) exactly when the machine is allowed to run. Which single gate do you use, and verify all four key combinations?

Forecast: "run only when both" = AND; but the STOP line is active-LOW, so we need output $0$ when both keys in → that's $\overline{A \cdot B}$ inverted... let's check carefully.

Step 1 — Translate the requirement. Allowed-to-run $= A \cdot B$ . STOP line must be $0$ when allowed, i.e. STOP $= \overline{A \cdot B}$ gives STOP $= 0$ only when $A \cdot B = 1$ . Why this step? Active-LOW means the asserted value is $0$ ; we assert STOP-release when both keys are in.

Step 2 — Pick the gate. STOP $= \overline{A \cdot B}$ is a NAND. Use one 2-input NAND: series NMOS, parallel PMOS. Why this step? Matches the boolean form directly, and NAND is the cheap/fast choice.

Step 3 — Sweep the keys. Why this step? An interlock must be safe in every degenerate case (no key, one key).

$A$	$B$	STOP $= \overline{A \cdot B}$	machine
0	0	1	stopped
0	1	1	stopped
1	0	1	stopped
1	1	0	runs

Verify: Machine runs in exactly the one row where both keys are inserted; any single-key or no-key case keeps STOP $= 1$ (safe). ✓

Example 9 — Cell C9: exam twist (reverse-engineer the function)

Worked example

Statement. You are shown a CMOS gate. Its PDN is 2 NMOS in parallel; its PUN is 2 PMOS in series. No label. What function $Y (A, B)$ is it, and prove it by the row $A = 0, B = 0$ ?

Forecast: parallel-NMOS = OR in the pull-down → this pulls $Y$ to $0$ on OR → so $Y = \overline{A + B}$ = NOR.

Step 1 — Read the PDN as its "pull-to-0" condition. Why this step? PDN sets when $Y = 0$ . Parallel NMOS conducts when $A + B = 1$ , so $Y = 0 ⟺ A + B = 1$ .

Step 2 — Invert to get $Y$ . $Y = 0$ when $A + B = 1$ ⇒ $Y = \overline{A + B}$ . That's NOR. The series-PMOS PUN is its De Morgan dual $\overset{ˉ}{A} \cdot \overset{ˉ}{B}$ — consistent. ✓ Why this step? Cross-check both networks agree; if they didn't, the drawing would be a broken (non-dual) gate.

Step 3 — Test $A = 0, B = 0$ . PDN: both NMOS gates $0$ → both off → PDN off. PUN: both PMOS gates $0$ → both on (series needs all on) → PUN on → $Y = 1$ .

Verify: $\overline{0 + 0} = \overline{0} = 1$ . ✓ Confirmed NOR.

Recall

NAND output is 0 in how many of its 4 rows? ::: Exactly one — when $A = B = 1$ . NOR output is 1 in how many rows? ::: Exactly one — when $A = B = 0$ . Total device width of a 2-input NAND at $k = 2$ (matched to inverter)? ::: $8$ ( $4$ NMOS + $4$ PMOS). Total width of the matched 2-input NOR at $k = 2$ ? ::: $10$ ( $2$ NMOS + $8$ PMOS). If PDN is parallel-NMOS and PUN is series-PMOS, the gate is…? ::: NOR. Number of short-circuit rows in any correct CMOS gate? ::: Zero (duality forbids both nets on).

Connections

3.2.03 CMOS NAND and NOR gate design (Hinglish) — parent topic these examples exercise.
CMOS Inverter — the 1-input base the sizing in Ex 6 is matched against.
De Morgan's Theorem — the identity Ex 5 uses to prove never-short/never-float.
MOSFET as a Switch — the conduct/off rule every example rests on.
Static Power and Short-Circuit Current — what Ex 5's zero-short-rows result buys you.
Logical Effort — quantifies the NAND-vs-NOR width gap from Ex 6.
Complex Gates (AOI/OAI) — where the 3-input generalisation of Ex 7 leads.