CMOS NAND and NOR gate design — Hinglish notes

3.2.3 · Hardware › CMOS Circuit Design

WHY does CMOS work this way?

WHY complementary? Kyunki agar dono networks ek saath conduct karen to short-circuit ( $V_{D D} \to GN D$ ) ho jaega aur static power burn hogi; agar koi bhi conduct na kare to output float ho jaega aur garbage hold karega. PUN aur PDN ko logical duals banana guarantee karta hai ki exactly-ek conduct kare.

HOW to build the NAND gate

Hum chahte hain $Y = \overline{A \cdot B}$ .

Step 1 — PDN: $Y = 0$ tab hi hoga jab $A \cdot B = 1$ , yaani jab $A$ AND $B$ dono HIGH hon. Why this step? AND ⇒ series NMOS. To $Y$ aur $GN D$ ke beech do NMOS in series lagao.

Step 2 — PUN (dual): series→parallel aur NMOS→PMOS swap karo. Why this step? $\overline{A \cdot B} = \overset{ˉ}{A} + \overset{ˉ}{B}$ , jo complements ka OR hai → parallel PMOS. $V_{D D}$ aur $Y$ ke beech do PMOS in parallel.

Step 3 — verify one input: $A = 1, B = 0$ . NMOS series toot gaya (B off) ⇒ PDN off. PMOS parallel: $B$ -PMOS ON hai (gate=0) ⇒ PUN $Y = 1$ pull karta hai. ✓ $\overline{1 \cdot 0} = 1$ se match karta hai.

Worked example NAND truth verification

A	B	PDN (series N)	PUN (parallel P)	Y
0	0	off	ON (both P)	1
0	1	off	ON (A-P)	1
1	0	off	ON (B-P)	1
1	1	ON	off	0

Har row mein exactly ek network conduct karta hai → na float, na short. ✓

HOW to build the NOR gate

Hum chahte hain $Y = \overline{A + B}$ .

Step 1 — PDN: $Y = 0$ jab $A + B = 1$ , yaani $A$ OR $B$ HIGH ho. Why? OR ⇒ parallel NMOS, $Y$ aur $GN D$ ke beech.

Step 2 — PUN (dual): $\overline{A + B} = \overset{ˉ}{A} \cdot \overset{ˉ}{B}$ ⇒ complements ka AND ⇒ $V_{D D}$ aur $Y$ ke beech series PMOS.

Sizing: WHY NAND is preferred over NOR

Recall Feynman: explain to a 12-year-old

Socho do paani ke pipes hain. Upar wale pipes paani neeche laate hain (woh "1" hai); neeche wale drains paani bahar nikaalte hain (woh "0" hai). Har pipe mein ek valve hai jo ek switch se control hota hai. NAND gate mein, drain side ke dono valves ek line mein hain — paani tab hi niklega jab tum dono switches kholo. To output "bhara" (1) rehta hai jab tak dono inputs on na hon. Upar wale pipes ulte tarike se lagaye hain (side-by-side) taaki jab bhi drain band ho, ek upar wala pipe hamesha khula rahe aur use bhara rakhe. Ye aise design kiya gaya hai ki tank kabhi ek saath bhi na bhare aur na nikle, aur kabhi khali-aur-khula na rahe.

Active Recall

Kaun sa transistor type pull-up network banata hai aur kyun?

PMOS, kyunki woh strong logic 1 pass karte hain (gate LOW hone par conduct karte hain), output ko

V_{D D}

ki taraf pull karte hain.

PDN mein series NMOS kaun sa logic operation implement karta hai?

AND (path tab hi conduct karta hai jab sab ON hon).

PDN mein parallel NMOS kaun sa logic implement karta hai?

OR (koi bhi ek ON path conduct karta hai).

2-input NAND ki transistor topology batao.

PDN: 2 NMOS in series; PUN: 2 PMOS in parallel.

2-input NOR ki transistor topology batao.

PDN: 2 NMOS in parallel; PUN: 2 PMOS in series.

CMOS mein NAND, NOR se preferred kyun hai?

NOR ko slow PMOS series mein chahiye (~

2 k

tak widen karna padta hai), jo speed/area hurt karta hai; NAND mein PMOS parallel rehte hain.

PDN se PUN banane ka duality rule batao.

NMOS↔PMOS aur series↔parallel swap karo (silicon mein De Morgan).

NAND mein A=1,B=0 ke liye kaun sa network conduct karta hai aur Y kya hai?

PUN conduct karta hai (B-PMOS on), Y=1.

PUN aur PDN ka logical duals hona zaroori kyun hai?

Taaki har input ke liye exactly ek conduct kare → na floating output aur na

V_{D D}

-to-GND short.

NOR PUN ka series PMOS hona kaun si De Morgan identity par based hai?

\overline{A + B} = \overset{ˉ}{A} \cdot \overset{ˉ}{B}

(AND ⇒ series).

Connections

CMOS Inverter — is PUN/PDN principle ka 1-input base case.
De Morgan's Theorem — woh algebra jo PUN/PDN duality guarantee karta hai.
MOSFET as a Switch — kyun NMOS strong 0 pass karta hai, PMOS strong 1.
Static Power and Short-Circuit Current — woh cheez jo complementary structure prevent karta hai.
Logical Effort — NAND vs NOR sizing penalty ko quantify karta hai.
Complex Gates (AOI/OAI) — series/parallel ko arbitrary functions tak generalize karta hai.