Level 5 — MasteryCMOS Circuit Design

CMOS Circuit Design

⏱ 75 minutes60 marksprintable — key stays hidden on paper

Time limit: 75 minutes Total marks: 60 Instructions: Answer all questions. Show all derivations. Use the alpha-power / long-channel MOSFET models as indicated. State assumptions clearly.

Question 1 — Static VTC, Noise Margins & Power (24 marks)

A CMOS inverter is built with a supply $V_{DD}=1.8\text{ V}$ . The transistors obey the long-channel model with threshold voltages $V_{Tn}=0.4\text{ V}$ , $|V_{Tp}|=0.4\text{ V}$ , and transconductance gains $k_n = \mu_n C_{ox}(W/L)_n$ , $k_p = \mu_p C_{ox}(W/L)_p$ .

(a) Derive the condition on the ratio $k_n/k_p$ that makes the inverter symmetric — i.e. places the switching threshold $V_M$ (where $V_{in}=V_{out}$ ) at exactly $V_{DD}/2$ . Assume both devices are saturated at $V_M$ . State the general expression for $V_M$ first, then specialise. (6)

(b) For the symmetric case, both devices are in saturation over a small window around $V_M$ . Model the gain in the transition region as $g = -\dfrac{g_{m,n}+g_{m,p}}{(g_{o,n}+g_{o,p})}$ . Taking the finite output conductance from channel-length modulation $g_o = \lambda I_D$ with $\lambda = 0.1\text{ V}^{-1}$ for both devices, and $g_m = \sqrt{2 k I_D}$ , and given the through-current at $V_M$ is $I_D = 50\ \mu\text{A}$ with $k_n=k_p=k=250\ \mu\text{A/V}^2$ , compute the small-signal voltage gain at $V_M$ . (5)

(c) Using the piecewise VTC approximation where $V_{IL}$ and $V_{IH}$ are the input voltages at which $\frac{dV_{out}}{dV_{in}}=-1$ , and given a symmetric VTC has been measured to give $V_{OH}=1.8\text{ V}$ , $V_{OL}=0\text{ V}$ , $V_{IL}=0.75\text{ V}$ , $V_{IH}=1.05\text{ V}$ , compute $NM_H$ and $NM_L$ . Comment on symmetry. (4)

(d) The inverter drives a load capacitance $C_L=15\text{ fF}$ and switches at frequency $f=200\text{ MHz}$ with activity factor $\alpha=0.4$ . Leakage current per gate is $I_{leak}=8\text{ nA}$ . Compute (i) dynamic power, (ii) static power, (iii) the total power, and (iv) state which dominates and by what factor. (6)

(e) Explain physically why short-circuit power exists in a real inverter but is neglected in parts (a)–(d), and name one design measure that reduces it. (3)

Question 2 — Pull-down networks, delay & power–delay product (22 marks)

Consider a CMOS gate implementing $Y = \overline{A\,(B+C)}$ .

(a) Design the transistor-level schematic: give the pull-down network (PDN) and the dual pull-up network (PUN), stating the series/parallel structure and total transistor count. Justify the PUN as the dual of the PDN. (6)

(b) Size the PDN transistors so the worst-case pull-down resistance equals that of a reference inverter NMOS of "unit" width $W$ and on-resistance $R$ . Give the width multiplier for each PDN transistor and identify the worst-case input pattern. (5)

(c) Model the worst-case discharge path as a chain of series transistors driving $C_L=20\text{ fF}$ . Using the Elmore delay for two equal series resistors $R_{eq}$ each with internal node capacitance $C_i=4\text{ fF}$ , the delay is $t_{pHL}=0.69\left(R_{eq}C_i + 2R_{eq}(C_i+C_L)\right)/2 \quad\text{(simplified 2-stage RC).}$ Actually use the standard Elmore form $t_p = 0.69\sum_i R_{i\to out}C_i$ . With two series NMOS each $R_{eq}=6\text{ k}\Omega$ , one intermediate node cap $C_x=4\text{ fF}$ and output cap $C_L=20\text{ fF}$ , compute $t_{pHL}$ . (6)

(d) Compute the power–delay product (PDP) for one switching event given $V_{DD}=1.8\text{ V}$ , $C_L=20\text{ fF}$ , using $E_{dyn}=C_L V_{DD}^2$ per full cycle and $t_p$ from part (c). Explain in one sentence why the PDP is the fundamental figure of merit rather than power or delay alone. (5)

Question 3 — Dynamic / Domino logic & transmission gates (14 marks)

(a) A dynamic (precharge–evaluate) CMOS gate suffers from charge sharing and cascading problems. Explain both, then prove that cascading dynamic gates directly (dynamic → dynamic) can produce an erroneous logic-1 glitch, and show how Domino logic fixes it. (6)

(b) A transmission gate passes a logic-1 from $V_{DD}=1.8\text{ V}$ . For an NMOS-only pass transistor with $V_{Tn}=0.4\text{ V}$ (including body effect raising it to $V_{Tn,eff}=0.55\text{ V}$ at the relevant node), find the maximum output "high" voltage. Then explain why the full transmission gate (parallel NMOS+PMOS) restores the full $V_{DD}$ , and give the resulting logic swing improvement. (5)

(c) Charge-sharing numeric: a dynamic node with $C_{dyn}=10\text{ fF}$ precharged to $1.8\text{ V}$ shares charge with an internal parasitic $C_{int}=3\text{ fF}$ initially at $0\text{ V}$ . Compute the settled voltage and state whether it could be misread as logic-0 if $V_{IL}=0.75\text{ V}$ . (3)

Answer keyMark scheme & solutions

Question 1

(a) At $V_M$ , $V_{in}=V_{out}$ ; both devices saturated, currents equal: $\tfrac12 k_n (V_M-V_{Tn})^2 = \tfrac12 k_p (V_{DD}-V_M-|V_{Tp}|)^2$ Solving for $V_M$ : $V_M=\frac{V_{Tn}+\sqrt{k_p/k_n}\,(V_{DD}-|V_{Tp}|)}{1+\sqrt{k_p/k_n}}\quad(2)$ Set $V_M=V_{DD}/2$ . With $V_{Tn}=|V_{Tp}|$ , symmetry requires $\sqrt{k_p/k_n}=1$ , i.e. $\boxed{k_n=k_p}\quad(2)$ Check: $V_M=\dfrac{0.4+1\cdot(1.8-0.4)}{2}=\dfrac{1.8}{2}=0.9=V_{DD}/2$ . ✓ (2) (Physically since $\mu_n>\mu_p$ , this needs $W_p/W_n=\mu_n/\mu_p$ .)

(b) $g_m=\sqrt{2kI_D}=\sqrt{2\cdot250\mu\cdot50\mu}=\sqrt{2.5\times10^{-8}}=1.5811\times10^{-4}$ S each (2). $g_{m,n}+g_{m,p}=3.1623\times10^{-4}$ S. $g_o=\lambda I_D=0.1\cdot50\mu=5\times10^{-6}$ S each; sum $=10^{-5}$ S (2). $g=-\frac{3.1623\times10^{-4}}{1.0\times10^{-5}}=-31.6$ Gain magnitude $\approx31.6$ . (1)

(c) $NM_H=V_{OH}-V_{IH}=1.8-1.05=0.75\text{ V}$ (2). $NM_L=V_{IL}-V_{OL}=0.75-0=0.75\text{ V}$ (2). Comment: $NM_H=NM_L=0.75$ V → symmetric noise margins, consistent with the symmetric $V_M=V_{DD}/2$ design.

(d) (i) $P_{dyn}=\alpha C_L V_{DD}^2 f = 0.4\cdot15\text{ fF}\cdot(1.8)^2\cdot200\text{ MHz}$ $=0.4\cdot15\times10^{-15}\cdot3.24\cdot2\times10^{8}=3.888\times10^{-6}$ W $=3.888\ \mu$ W (2). (ii) $P_{stat}=V_{DD}I_{leak}=1.8\cdot8\times10^{-9}=1.44\times10^{-8}$ W $=14.4\text{ nW}$ (2). (iii) $P_{tot}=3.888\ \mu\text{W}+0.0144\ \mu\text{W}=3.902\ \mu$ W (1). (iv) Dynamic dominates by factor $3.888\mu/14.4n\approx270\times$ (1).

(e) Short-circuit (crowbar) power occurs during the input transition when $V_{Tn}<V_{in}<V_{DD}-|V_{Tp}|$ , so both NMOS and PMOS conduct simultaneously providing a direct $V_{DD}$ →GND path (2). It is neglected in the ideal $\alpha C V^2 f$ model which assumes instantaneous switching. Reducing it: keep input rise/fall times short (fast edges) / balance driver strengths (1).

Question 2

(a) $Y=\overline{A(B+C)}$ . PDN conducts (pulls low) when $A(B+C)=1$ : NMOS A in series with (NMOS B parallel NMOS C) (2). PUN is the dual: PMOS A in parallel with (PMOS B series PMOS C) (2). Total = 6 transistors. Dual: series in PDN ↔ parallel in PUN and vice-versa, guaranteeing complementary conduction so exactly one network is on for any input (2).

(b) Reference NMOS width $W$ gives resistance $R$ . Series devices double effective resistance, so to match $R$ each series element must be sized $2W$ . In the PDN the worst path is A-then-(B or C): two series transistors. Size A = $2W$ , and B, C each $=2W$ (so any single ON parallel branch of resistance $R$ combines with A to $2R$ ... to meet unit $R$ we set A $=2W$ , B $=2W$ , C $=2W$ ) (3). Worst-case pattern: only one of B/C high (say $B=1,C=0$ , $A=1$ ) → single series path B alone (no parallel help) → highest resistance (2).

(c) Elmore: node $x$ between the two series NMOS. $t_{pHL}=0.69\big[R_{eq}(C_x+C_L)+(R_{eq}+R_{eq})C_L\big]$ — resistance from each cap to output:

$C_x$ sees $R_{eq}$ (one transistor to output): $R_{eq}C_x$
$C_L$ sees $2R_{eq}$ (both transistors): $2R_{eq}C_L$ $t_{pHL}=0.69\,[R_{eq}C_x + 2R_{eq}C_L]$ $=0.69\,[6\text{k}\cdot4\text{fF}+2\cdot6\text{k}\cdot20\text{fF}]$ $=0.69\,[24\times10^{-15}+240\times10^{-15}]$ (V·s units→) $=0.69\cdot264\times10^{-15}\ \text{(k}\Omega\cdot\text{fF}=10^{-12}\text{s})$ $R\text{k}\Omega\cdot C\text{fF}: 6000\cdot4\times10^{-15}=2.4\times10^{-11}$ , $2\cdot6000\cdot20\times10^{-15}=2.4\times10^{-10}$ ; sum $=2.64\times10^{-10}$ . $t_{pHL}=0.69\cdot2.64\times10^{-10}=1.822\times10^{-10}\text{ s}=182.2\text{ ps}$ (6).

(d) $E_{dyn}=C_L V_{DD}^2=20\text{ fF}\cdot3.24=6.48\times10^{-14}$ J $=64.8$ fJ (2). $PDP=E_{dyn}$ per switching event is the energy $=64.8$ fJ; equivalently using $P=E f$ and $PDP=P\cdot t_p$ gives energy per operation. (2) PDP is fundamental because it measures energy per operation, allowing fair comparison of technologies that trade power against speed (you can always lower power by slowing down) (1).

Question 3

(a) Charge sharing: during evaluate, the precharged output node redistributes charge with internal parasitic caps of the PDN, dropping the dynamic node voltage even when the logic should hold high, possibly to a false 0 (2). Cascading: a dynamic gate's output starts precharged HIGH; during evaluate it may fall, but before it falls the following dynamic gate (also precharged, input HIGH) may erroneously discharge → non-monotonic glitch producing wrong 1→0 (2). Domino inserts a static inverter after each dynamic stage; its output is precharged LOW, so during evaluate inputs to the next stage can only make 0→1 transitions (monotonically rising), which cannot falsely trigger a precharged-high dynamic node (2).

(b) NMOS passes high only up to $V_{DD}-V_{Tn,eff}=1.8-0.55=1.25\text{ V}$ (2) — the transistor cuts off when $V_{GS}=V_{DD}-V_{out}=V_{Tn,eff}$ . This is a degraded high (threshold drop) (1). The parallel PMOS passes a strong 1 (no threshold drop for high), so the transmission gate restores the output to full $1.8\text{ V}$ (1). Swing improves from $0$ – $1.25$ V to $0$ – $1.8$ V, restoring full noise margin (1).

(c) Charge conservation: $V_f=\dfrac{C_{dyn}V_{pre}}{C_{dyn}+C_{int}}=\dfrac{10\cdot1.8}{13}=1.3846\text{ V}$ (2). Since $1.385\text{ V}>V_{IL}=0.75\text{ V}$ , it is still read as logic-1 — no error here, though larger $C_{int}$ would cause failure (1).

[
{"claim":"Q1a symmetric V_M equals VDD/2 = 0.9V","code":"VDD,VTn,VTp=1.8,0.4,0.4; VM=(VTn+1*(VDD-VTp))/(1+1); result = (VM==Rational(9,10)) or abs(float(VM)-0.9)<1e-9"},
{"claim":"Q1b gain magnitude approx 31.6","code":"k=250e-6; ID=50e-6; gm=sqrt(2*k*ID); go=0.1*ID; gain=(2*gm)/(2*go); result = abs(float(gain)-31.6228)<0.01"},
{"claim":"Q1d dynamic power 3.888 uW","code":"P=0.4*15e-15*(1.8**2)*200e6; result = abs(float(P)-3.888e-6)<1e-9"},
{"claim":"Q2c tpHL approx 182.2 ps","code":"Req=6000; Cx=4e-15; CL=20e-15; t=0.69*(Req*Cx+2*Req*CL); result = abs(float(t)-1.8216e-10)<1e-12"},
{"claim":"Q2d energy per event 64.8 fJ","code":"E=20e-15*(1.8**2); result = abs(float(E)-64.8e-15)<1e-18"},
{"claim":"Q3c charge sharing settles to 1.3846 V","code":"Vf=Rational(10*18,13*10); result = abs(float(Vf)-1.38462)<1e-4"}
]