Level 4 — ApplicationCMOS Circuit Design

CMOS Circuit Design

⏱ 60 minutes60 marksprintable — key stays hidden on paper

Level: 4 — Application (novel problems, no hints) Time limit: 60 minutes Total marks: 60

Assume the following unless a question states otherwise:

Supply voltage $V_{DD} = 1.8\text{ V}$
NMOS threshold $V_{Tn} = 0.4\text{ V}$ , PMOS threshold $|V_{Tp}| = 0.4\text{ V}$
Unit transistor transconductance $k_n' (W/L) = k_p' (W/L) = 200\ \mu\text{A/V}^2$ where noted

Question 1 — Compound gate synthesis and sizing (14 marks)

A designer needs a single static CMOS complex gate implementing $Y = \overline{A\cdot(B + C)}$

(a) Draw (describe transistor-by-transistor) the pull-down network (PDN) and pull-up network (PUN), stating series/parallel arrangement for each. (4)

(b) The reference inverter uses NMOS width $W_n = 1\ \mu\text{m}$ and PMOS width $W_p = 2\ \mu\text{m}$ (to equalise drive, given electron mobility $= 2\times$ hole mobility). Size every transistor in your complex gate so its worst-case pull-up and pull-down strengths equal those of the reference inverter. Give each transistor width. (7)

(c) State which input assignment gives the worst-case (slowest) charging path through the PUN, and justify. (3)

Question 2 — Noise margins from a piecewise VTC (12 marks)

Measurements on a fabricated inverter give the voltage transfer characteristic slope $= -1$ at two points:

$V_{IL} = 0.70\text{ V}$ with output $V_{OH} = 1.70\text{ V}$
$V_{IH} = 1.05\text{ V}$ with output $V_{OL} = 0.12\text{ V}$

(a) Compute $NM_H$ and $NM_L$ . (4)

(b) This inverter drives an identical stage across a bus that couples in a noise spike of amplitude $0.5\text{ V}$ onto a logic-LOW line. Will the receiving gate misinterpret the level? Justify numerically. (3)

(c) The transition (undefined) region width is $V_{IH}-V_{IL}$ . A second design has the same $V_{OH}, V_{OL}$ but a steeper VTC giving $V_{IL}=0.80$ , $V_{IH}=0.95\text{ V}$ . Compare both noise margins and the transition width, and explain the design trade-off implied. (5)

Question 3 — Dynamic vs static power and PDP (12 marks)

A CMOS block on a $1.8\text{ V}$ supply switches at $f = 500\text{ MHz}$ with an average node switching activity $\alpha = 0.15$ . Total switched capacitance $C_L = 40\text{ pF}$ . Static leakage current is $I_{leak} = 8\ \mu\text{A}$ .

(a) Compute the dynamic power and static power. State which dominates. (5)

(b) Total propagation delay through the critical path is $t_p = 180\text{ ps}$ . Compute the power–delay product using total power. (3)

(c) The designer lowers $V_{DD}$ to $1.2\text{ V}$ . Assuming dynamic power scales as $V_{DD}^2$ , leakage scales linearly with $V_{DD}$ , and delay increases by a factor $1.7$ , recompute total power and PDP. Comment on whether voltage scaling improved the PDP. (4)

Question 4 — Dynamic / Domino logic evaluation (12 marks)

Consider a footed dynamic logic gate evaluating $F = \overline{A\cdot B \cdot C}$ (i.e. a dynamic NAND-like structure) with a clock $\phi$ .

(a) Describe the precharge and evaluate phases, and explain what the "foot" (clocked NMOS) transistor prevents. (4)

(b) Explain why a plain dynamic gate cannot be directly cascaded to another dynamic gate, and how converting to domino logic fixes this. State one function limitation domino logic introduces. (5)

(c) During evaluation the dynamic node ( $C_{node}=15\text{ fF}$ , precharged to $1.8\text{ V}$ ) suffers charge sharing with an internal node ( $C_{int}=6\text{ fF}$ , initially at $0\text{ V}$ ) when only the top transistor turns on. Compute the resulting dynamic node voltage and state whether this risks a false evaluation if the gate's switching threshold is $0.9\text{ V}$ . (3)

Question 5 — Pass-transistor / transmission-gate mux delay (10 marks)

A 2:1 multiplexer is built from two transmission gates (TGs) selecting between inputs $D_0, D_1$ .

(a) Explain why a single NMOS pass transistor passing a logic HIGH suffers a "threshold drop", and how the TG removes it. (4)

(b) Each TG can be modelled as a resistance $R_{TG}=1.2\text{ k}\Omega$ driving the output load $C_{out}=25\text{ fF}$ plus a following inverter input $C_{in}=10\text{ fF}$ . Using the Elmore delay estimate $t_p = 0.69\,R\,C$ , compute the propagation delay from a TG input to the output node. (4)

(c) State one reason a chain of $N$ pass transistors gives delay growing as $N^2$ , and how buffering breaks this. (2)

Answer keyMark scheme & solutions

Question 1

(a) Function $Y=\overline{A(B+C)}$ . PDN pulls low when $A(B+C)=1$ .

PDN (NMOS): transistor $A$ in series with the parallel combination of $B$ and $C$ . (Series $A$ – parallel $\{B,C\}$ .) (2)
PUN (PMOS): dual network — $A$ in parallel with the series combination of $B$ and $C$ . (Parallel $A$ – series $\{B,C\}$ .) (2)

(b) Reference: $W_n=1\ \mu\text{m}$ , $W_p=2\ \mu\text{m}$ .

PDN sizing (match to single reference NMOS of width 1):

The series path is $A$ then ( $B$ ∥ $C$ ). Worst-case pull-down is a series stack of two transistors → each series device doubled to keep the effective series resistance equal to one unit NMOS.
$A$ : series with the $B/C$ stage → width $= 2\ \mu\text{m}$ .
$B$ and $C$ are in parallel, but the worst case (only one of B,C on) must still drive: each must be sized as a series element → width $= 2\ \mu\text{m}$ each. (3)

PUN sizing (match to reference PMOS width 2):

$B$ and $C$ in series → each doubled: $2\times2 = 4\ \mu\text{m}$ each.
$A$ in parallel (single device path) → $2\ \mu\text{m}$ . (3)

Summary table: $W_{A,n}=2$ , $W_{B,n}=W_{C,n}=2$ ; $W_{A,p}=2$ , $W_{B,p}=W_{C,p}=4$ (µm). (1)

(c) Worst-case (slowest) PUN charging: the path through the series $B$ – $C$ PMOS stack, which occurs when $A=1$ (so the parallel $A$ PMOS is OFF) and $B=C=0$ . Charging must flow through two stacked PMOS in series → highest resistance → slowest rise. (3)

Question 2

(a) $NM_H = V_{OH} - V_{IH} = 1.70 - 1.05 = 0.65\text{ V}$ $NM_L = V_{IL} - V_{OL} = 0.70 - 0.12 = 0.58\text{ V}$ (4)

(b) A logic-LOW line sits at $V_{OL}=0.12\text{ V}$ . Adding a $0.5\text{ V}$ spike gives $0.62\text{ V}$ . Compare to $V_{IL}=0.70\text{ V}$ : since $0.62 < 0.70\text{ V}$ , the input is still interpreted as valid LOW. Equivalently the spike ( $0.5$ ) is less than $NM_L=0.58$ , so no misinterpretation. (3)

(c) Design 2: $NM_H = 1.70-0.95 = 0.75\text{ V}$ , $NM_L = 0.80-0.12 = 0.68\text{ V}$ .

Transition width: design 1 $=1.05-0.70=0.35\text{ V}$ ; design 2 $=0.95-0.80=0.15\text{ V}$ . (2)
Design 2 has larger noise margins and narrower transition (steeper VTC → higher gain). (1)
Trade-off: steeper VTC (higher gain in transition) improves noise immunity but a higher-gain, higher- $g_m$ stage generally costs larger devices / more current / more sensitivity to process variation, and a sharper transition can increase short-circuit power during switching. (2)

Question 3

(a) $P_{dyn} = \alpha C_L V_{DD}^2 f = 0.15 \times 40\times10^{-12} \times 1.8^2 \times 500\times10^6$ $= 0.15\times40\text{p}\times3.24\times0.5\text{G} = 9.72\times10^{-3}\text{ W} = 9.72\text{ mW}$ (3) $P_{stat} = I_{leak} V_{DD} = 8\times10^{-6}\times1.8 = 14.4\ \mu\text{W}$ (1) Dynamic power dominates ( $9.72\text{ mW} \gg 14.4\ \mu\text{W}$ ). (1)

(b) $P_{tot} = 9.72\text{ mW} + 0.0144\text{ mW} = 9.7344\text{ mW}$ . $PDP = P_{tot}\times t_p = 9.7344\times10^{-3}\times180\times10^{-12} = 1.752\times10^{-12}\text{ J} \approx 1.75\text{ pJ}$ (3)

(c) Scaling to $V_{DD}=1.2\text{ V}$ (factor $1.2/1.8 = 0.6667$ ):

$P_{dyn}' = 9.72\times(1.2/1.8)^2 = 9.72\times0.4444 = 4.32\text{ mW}$
$P_{stat}' = 14.4\times0.6667 = 9.6\ \mu\text{W}$
$P_{tot}' = 4.3296\text{ mW}$
$t_p' = 180\times1.7 = 306\text{ ps}$
$PDP' = 4.3296\text{ mW}\times306\text{ ps} = 1.325\times10^{-12}\text{ J} \approx 1.32\text{ pJ}$ (3)

Comparison: PDP falls from $1.75$ to $1.32\text{ pJ}$ , so voltage scaling improved the PDP despite slower speed (power drops with $V^2$ faster than delay rises here). (1)

Question 4

(a) Precharge ( $\phi=0$ ): the top PMOS turns on, charging the dynamic output node to $V_{DD}$ ; the foot NMOS is OFF so no DC path. Evaluate ( $\phi=1$ ): PMOS off, foot NMOS on; if the input NMOS stack conducts, the node discharges (output goes LOW), else it holds HIGH. The foot transistor prevents a short-circuit / static discharge path during precharge (ensures no crowbar current while the PMOS charges the node, and prevents evaluation before the clock is high). (4)

(b) During precharge all dynamic nodes are HIGH. If gate G1's output (HIGH) feeds gate G2's input, in evaluate phase G2 may begin discharging before G1 has decided to fall — a $1\to0$ transition at G1's output can wrongly trigger G2, but dynamic gates only work with monotonic $0\to1$ inputs during evaluate. A dynamic input starting HIGH violates monotonicity → false discharge. (2) Domino fix: add a static inverter after each dynamic node. Its output is LOW after precharge and can only rise $0\to1$ during evaluate — a monotonically rising signal — which is a legal input to the next dynamic stage. (2) Limitation: because of the inverter, each domino stage is non-inverting; domino logic can only realise non-inverting functions (cannot directly build inverting logic without extra techniques). (1)

(c) Charge sharing (conservation of charge): $V_{node} = \frac{C_{node}V_{DD} + C_{int}\cdot 0}{C_{node}+C_{int}} = \frac{15\times1.8}{15+6} = \frac{27}{21} = 1.286\text{ V}$ (2) Since $1.286\text{ V} > 0.9\text{ V}$ (the switching threshold), the node stays above threshold → no false evaluation (safe, but margin is reduced). (1)

Question 5

(a) An NMOS passing a HIGH conducts only while $V_{GS} > V_{Tn}$ ; as the source (output) rises, $V_{GS}$ shrinks and the device shuts off when the output reaches $V_{DD}-V_{Tn}$ . Hence the output cannot exceed $V_{DD}-V_{Tn}$ (a "threshold drop", weak "1"). The transmission gate adds a parallel PMOS driven by the complementary control; the PMOS passes a strong HIGH (loses no $V_{Tp}$ near $V_{DD}$ ) while the NMOS passes a strong LOW, so together they deliver a full-swing $0$ to $V_{DD}$ . (4)

(b) Total load $C = C_{out}+C_{in} = 25+10 = 35\text{ fF}$ . $t_p = 0.69\,R_{TG}\,C = 0.69\times1200\times35\times10^{-15}$ $= 0.69\times1200\times35\text{f} = 2.898\times10^{-11}\text{ s} \approx 29\text{ ps}$ (4)

(c) A chain of $N$ pass transistors forms a distributed RC ladder; the Elmore delay sums $R$ - $C$ products over all upstream sections, giving $\propto \sum_{i=1}^{N} i \approx N^2/2$ → quadratic growth. Inserting buffers/inverters every few stages restores full logic levels and breaks the ladder into segments, making total delay grow linearly with $N$ . (2)

[
  {"claim":"Q2 noise margins NMH=0.65 and NML=0.58",
   "code":"VOH,VIH,VIL,VOL=1.70,1.05,0.70,0.12; NMH=VOH-VIH; NML=VIL-VOL; result=(abs(NMH-0.65)<1e-9 and abs(NML-0.58)<1e-9)"},
  {"claim":"Q3a dynamic power = 9.72 mW",
   "code":"Pdyn=0.15*40e-12*1.8**2*500e6; result=abs(Pdyn-9.72e-3)<1e-9"},
  {"claim":"Q3c scaled PDP approx 1.325 pJ",
   "code":"Pd=9.72e-3*(1.2/1.8)**2; Ps=8e-6*1.2; Pt=Pd+Ps; tp=180e-12*1.7; PDP=Pt*tp; result=abs(PDP-1.325e-12)<5e-15"},
  {"claim":"Q4c charge-sharing node voltage = 27/21 V",
   "code":"V=(15*1.8+6*0)/(15+6); result=abs(V-27/21)<1e-9 and V>0.9"},
  {"claim":"Q5b TG delay approx 29 ps",
   "code":"tp=0.69*1200*35e-15; result=abs(tp-2.898e-11)<1e-13"}
]