CMOS Circuit Design

Question 1

(a) (4 marks)

• Schematic: PMOS (source→$V_{DD}$, drain→output) on top, NMOS (source→GND, drain→output) on bottom, gates tied to $V_{in}$, output between drains. (2)
• PMOS = pull-up network (PUN); NMOS = pull-down network (PDN). (1)
• Why no static path: for any static input one transistor is ON and the other OFF (complementary). When $V_{in}=0$: NMOS off, PMOS on → output high with no path to GND. When $V_{in}=V_{DD}$: PMOS off, NMOS on → output low with no path to $V_{DD}$. Only during switching are both briefly ON → hence ideally zero static current. (1)

(b) (5 marks) — 1 mark per correct region row.

(c) (3 marks) Both in saturation, currents equal: $\frac{k_n}{2}(V_M-V_{Tn})^2 = \frac{k_p}{2}(V_{DD}-V_M-|V_{Tp}|)^2$. (1) Take root: $\sqrt{k_n}(V_M-V_{Tn}) = \sqrt{k_p}(V_{DD}-V_M-|V_{Tp}|)$. Solve: $V_M = \frac{V_{Tn} + \sqrt{k_p/k_n}\,(V_{DD}-|V_{Tp}|)}{1+\sqrt{k_p/k_n}}$ (2)

Question 2

(a) PDN (3): PDN conducts when $Y=0$, i.e. when $A(B+C)=1$. So NMOS: transistor $A$ in series with the parallel combination of $B$ and $C$. (A–[B∥C] series stack to GND.) (3)

(b) PUN (3): Dual of PDN: series→parallel, parallel→series. PMOS: transistor $A$ in parallel with the series combination of $B$ and $C$. (A ∥ [B–C series] to $V_{DD}$.) (3)

(c) (4):

• Transistor count: 3 NMOS + 3 PMOS = 6 transistors. (2)
• Worst-case path: the longest series chain in the PDN is $A$ in series with $B$ (or $A$–$C$) = 2 transistors in series → highest resistance, hence slowest fall. The parallel B∥C halves that leg's resistance but the A–B (or A–C) series path of length 2 sets worst-case pull-down delay. (2)

Question 3

(a) (5): Per output rising transition, charge $Q=C_LV_{DD}$ is drawn from supply; energy from supply $=Q V_{DD}=C_LV_{DD}^2$, of which half stored on $C_L$ ($\tfrac12 C_LV_{DD}^2$), half dissipated in PMOS. On falling transition the stored $\tfrac12 C_LV_{DD}^2$ dissipates in NMOS. So a full cycle dissipates $C_LV_{DD}^2$. (3) If transitions occur at effective rate $\alpha f$ (α = probability of a switching event per clock cycle = activity factor), then $P_{dyn}=\alpha C_L V_{DD}^2 f$. α accounts for the fact that not every node toggles every cycle. (2)

(b) (5): $P_{dyn}=\alpha C_L V_{DD}^2 f = 0.15\times150\times10^{-15}\times(1.2)^2\times500\times10^6$ $=0.15\times150e{-15}\times1.44\times5e8 = 1.62\times10^{-5}\,\text{W}=16.2\,\mu\text{W}$. (2) $P_{static}=I_{leak}V_{DD}=20\times10^{-9}\times1.2=2.4\times10^{-8}=24\,\text{nW}$. (2) $P_{total}=16.2\,\mu\text{W}+0.024\,\mu\text{W}\approx 16.224\,\mu\text{W}$. (1)

Question 4

(a) (4): $NM_H=V_{OH}-V_{IH}$ = margin by which a driven HIGH exceeds the max input still read as HIGH → tolerable negative noise on a logic-1. $NM_L=V_{IL}-V_{OL}$ = margin by which max input read as LOW exceeds a driven LOW → tolerable positive noise on a logic-0. Larger margins → more noise immunity. (4)

(b) (3): $NM_H=1.15-0.75=0.40\,\text{V}$. (1.5) $NM_L=0.45-0.05=0.40\,\text{V}$. (1.5)

(Note: with these numbers margins are equal at 0.40 V.)

(c) (3): Margins are equal here (0.40 V each) so the gate is balanced; if asymmetry existed, the smaller margin identifies the weaker polarity. To shift $V_M$ (and rebalance): change the PMOS/NMOS width ratio — increasing PMOS width (larger $k_p/k_n$) raises $V_M$ (improves $NM_L$); increasing NMOS width lowers $V_M$ (improves $NM_H$). (3) (Full marks for correct reasoning + one valid sizing change.)

Question 5

(a) (4): Output falls from $V_{DD}$: $V_{out}(t)=V_{DD}e^{-t/R_{eq}C_L}$. $t_p$ defined at $V_{out}=V_{DD}/2$: $\tfrac12 V_{DD}=V_{DD}e^{-t_p/R_{eq}C_L}\Rightarrow e^{-t_p/\tau}=1/2 \Rightarrow t_p=\tau\ln 2 = 0.69\,R_{eq}C_L$. (4)

(b) (6): $t_p=0.69\times8000\times30\times10^{-15}=0.69\times2.4\times10^{-10}=1.656\times10^{-10}=165.6\,\text{ps}$. (2) $E=C_LV_{DD}^2=30\times10^{-15}\times1.0^2=3.0\times10^{-14}\,\text{J}=30\,\text{fJ}$. (2) $PDP=E=30\,\text{fJ}$ (energy per switching event). (1) Comment: PDP measures the energy cost per operation — a figure of merit trading speed against power; lower PDP = more efficient technology. (1)

Question 6

(a) (3): Precharge phase (clk=0): PMOS precharge transistor pulls dynamic node to $V_{DD}$; the clocked evaluate NMOS (foot) is off so no discharge. Evaluate phase (clk=1): precharge PMOS off, foot NMOS on; the PDN either discharges the node (output→0) or holds it high depending on inputs. (3)

(b) (5):

• Charge sharing: during evaluate, charge on the precharged node redistributes onto internal parasitic capacitances of the PDN if intermediate nodes were low, dropping the output voltage possibly below threshold → false 0. (1.5)
• Cascading problem: a dynamic gate output is only valid HIGH at start of evaluate; if it feeds another dynamic gate, a momentary high (glitch) during evaluation can incorrectly discharge the next stage before the driving gate settles low → cannot cascade dynamic gates directly. (1.5)
• Domino fix: insert a static inverter after each dynamic node. The dynamic node is precharged HIGH, so the buffered output is LOW at start of evaluate; it can only make a monotonic low→high transition, which cannot falsely discharge the following gate — so gates cascade "like dominoes". (1.5)
• Restriction: domino gates are non-inverting only (the static inverter fixes polarity), so inverting functions require alternative structures/logic restructuring. (0.5)

[
  {"claim":"Q3 dynamic power = 16.2 uW","code":"P=0.15*150e-15*(1.2**2)*500e6; result = abs(P-16.2e-6)<1e-9"},
  {"claim":"Q3 static power = 24 nW","code":"Ps=20e-9*1.2; result = abs(Ps-24e-9)<1e-12"},
  {"claim":"Q5 tp = 165.6 ps","code":"tp=0.69*8000*30e-15; result = abs(tp-165.6e-12)<1e-13"},
  {"claim":"Q5 energy PDP = 30 fJ","code":"E=30e-15*(1.0**2); result = abs(E-30e-15)<1e-18"},
  {"claim":"Q4 noise margins both 0.40 V","code":"NMH=1.15-0.75; NML=0.45-0.05; result = abs(NMH-0.40)<1e-9 and abs(NML-0.40)<1e-9"}
]