Pull-up and pull-down networks

A CMOS gate is a switch factory. Two teams of transistors fight over the output node: one team pulls it HIGH, the other pulls it LOW — and by design, never both at once.

Core Idea

WHY PMOS pulls up, NMOS pulls down (from first principles)

HOW to build the networks: the duality rules

The PUN and PDN are duals. Build one from the Boolean function, then get the other by De Morgan.

Formula Deriving structure from the logic

A CMOS gate computes an inverting function $Y = \overline{f(\text{inputs})}$ .

Step 1 — PDN (pulls output to 0 when $Y=0$ , i.e. when $f=1$ ):

Series NMOS ⇒ AND of inputs (both must be ON to conduct).
Parallel NMOS ⇒ OR of inputs (either ON conducts).

Step 2 — PUN is the topological dual:

series in PDN ⟷ parallel in PUN
parallel in PDN ⟷ series in PUN
Each NMOS (input $A$ ) maps to a PMOS with the same input $A$ (the bubble/complement is built in because PMOS turns on with a low input).

Why this works: By De Morgan, $\overline{A\cdot B} = \bar A + \bar B$ and $\overline{A+B} = \bar A \cdot \bar B$ . Series↔AND and parallel↔OR, so swapping series/parallel is applying De Morgan — automatically giving the complementary conduction condition.

Let $g_{PDN}$ = "PDN conducts" and $g_{PUN}$ = "PUN conducts". Correct design requires: $g_{PDN} = \overline{g_{PUN}} \quad\text{(complementary: never both, never neither)}$ and the output is $Y = \overline{g_{PDN}}$ (output is high exactly when the PDN is OFF and the PUN is ON).

Worked Example 1 — the Inverter

Function: $Y = \bar A$ .

PDN: output must go LOW when $A=1$ . One NMOS, gate $=A$ , between $Y$ and GND. Why this step? $f = A$ , so a single series device controlled by $A$ .
PUN (dual): single PMOS, gate $=A$ , between $V_{DD}$ and $Y$ . Why? Dual of one series device is one device; PMOS turns on when $A=0$ , pulling output high.
Check: $A=0 \Rightarrow$ PMOS ON, NMOS OFF ⇒ $Y=1$ . $A=1 \Rightarrow$ NMOS ON ⇒ $Y=0$ . ✔ Complementary.

Worked Example 2 — 2-input NAND

Function: $Y = \overline{A\cdot B}$ , so $f = A\cdot B$ .

PDN: output LOW only when $A\cdot B = 1$ ⇒ need both ON ⇒ two NMOS in series, gates $A$ and $B$ . Why? AND ⇒ series.
PUN (dual): series→parallel ⇒ two PMOS in parallel, gates $A$ , $B$ . Why? $\overline{A B}=\bar A+\bar B$ ⇒ output high if either input is low ⇒ PMOS in parallel each pull up.
Check $A=B=1$ : series NMOS conducts → $Y=0$ ; both PMOS off. Any other combo: at least one PMOS on → $Y=1$ . ✔

Worked Example 3 — 2-input NOR

Function: $Y = \overline{A+B}$ , so $f = A+B$ .

PDN: LOW when $A+B=1$ ⇒ either ON pulls low ⇒ two NMOS in parallel. Why? OR ⇒ parallel.
PUN (dual): parallel→series ⇒ two PMOS in series. Why? $\overline{A+B}=\bar A\bar B$ ⇒ output high only when both inputs low ⇒ series PMOS.
Check $A=B=0$ : both PMOS on (series) → $Y=1$ ; both NMOS off. Else some NMOS on → $Y=0$ . ✔

Worked Example 4 — Compound gate (AOI)

Function: $Y = \overline{(A\cdot B) + C}$ .

PDN: $f=(AB)+C$ . $AB$ ⇒ series pair ( $A$ then $B$ ); that whole branch in parallel with a single NMOS $C$ (the OR).
PUN (dual): OR→series, AND→parallel: PMOS $C$ in series with (PMOS $A$ ∥ PMOS $B$ ).
Why one gate does this: CMOS compound gates implement any $\overline{\text{AND-OR}}$ (AOI) or $\overline{\text{OR-AND}}$ (OAI) form in a single stage — cheaper and faster than chaining NANDs.

Active Recall

PUN is made of which transistor type and connects output to what?

PMOS transistors, connecting output to

V_{DD}

PDN is made of which transistor type and connects output to what?

NMOS transistors, connecting output to ground.

Why use PMOS for pull-up and NMOS for pull-down?

PMOS passes a strong 1, NMOS passes a strong 0; placing each where it excels gives rail-to-rail output.

Series NMOS in the PDN implements which Boolean operation?

AND (both must be ON to conduct).

Parallel NMOS in the PDN implements which Boolean operation?

OR (either ON conducts).

How is the PUN topology obtained from the PDN?

It is the dual — swap series↔parallel, same input on the matching PMOS.

What is the golden design rule for PUN/PDN?

For every input, exactly one network conducts:

g_{PDN}=\overline{g_{PUN}}

For a 2-input NAND, describe PDN and PUN.

PDN: 2 NMOS in series; PUN: 2 PMOS in parallel.

For a 2-input NOR, describe PDN and PUN.

PDN: 2 NMOS in parallel; PUN: 2 PMOS in series.

Why is a degraded '1' from NMOS bad?

Output caps at

V_{DD}-V_{tn}

, cutting noise margin and possibly leaking static current in the next stage.

What logic form does a static CMOS gate always compute?

An inverting function

Y=\overline{f}

(AOI/OAI, inherently inverting).

Why no static power in static CMOS?

The complementary networks never conduct simultaneously, so there's no continuous

V_{DD}

-to-GND path.

Connections

CMOS Inverter — simplest PUN/PDN pair.
NAND and NOR gates — series/parallel duality in action.
De Morgan's Theorem — mathematical basis of the duality rule.
Threshold Voltage and Body Effect — why NMOS gives degraded 1.
Static vs Dynamic Power — why complementary design saves power.
Pass Transistor Logic — what happens when you break the strong/weak rule.

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, CMOS gate ke andar do teams hoti hain jo output wire pe control karti hain. Ek team PUN (Pull-Up Network) hai jo PMOS transistors se bani hoti hai aur output ko $V_{DD}$ tak, yaani logic 1 tak, kheench ke le jaati hai. Doosri team PDN (Pull-Down Network) hai jo NMOS transistors se bani hoti hai aur output ko ground, yaani 0 tak, kheenchti hai. Rule bilkul simple hai: kisi bhi input combination pe sirf ek hi network ON hoga — kabhi dono nahi, kabhi koi nahi.

Ab sawaal — PMOS upar kyun aur NMOS neeche kyun? Kyunki NMOS ek strong 0 pass karta hai par ek weak 1 (output $V_{DD}-V_{tn}$ tak hi jaata hai, poora nahi). PMOS ulta — strong 1, weak 0. Toh har transistor ko wahi kaam do jismein woh best hai: NMOS ko pull-down, PMOS ko pull-up. Isse output hamesha clean full 1 ya full 0 milta hai, aur beech mein koi degraded value nahi.

Networks banane ka trick duality hai. PDN mein series NMOS = AND, parallel NMOS = OR. PUN uska ulta hota hai — series ko parallel bana do, parallel ko series. Yeh actually De Morgan ka law hi hai chhupa hua. Jaise NAND ( $\overline{AB}$ ): PDN mein do NMOS series, PUN mein do PMOS parallel. NOR ( $\overline{A+B}$ ): PDN mein do NMOS parallel, PUN mein do PMOS series. Bas ulta ho gaya!

Yeh cheez matter kyun karti hai? Kyunki jab ek hi network conduct karta hai, tab $V_{DD}$ se ground tak koi seedha current path nahi banta — matlab static power almost zero. Isiliye CMOS ne baaki technologies ko peeche chhod diya. Exam aur design dono mein: pehle function likho, PDN banao (AND=series, OR=parallel), phir dual leke PUN banao. Ho gaya kaam.

Core Idea

WHY PMOS pulls up, NMOS pulls down (from first principles)

HOW to build the networks: the duality rules

Worked Example 1 — the Inverter

Worked Example 2 — 2-input NAND

Worked Example 3 — 2-input NOR

Worked Example 4 — Compound gate (AOI)

Active Recall

Connections

Concept Map

Hinglish (regional understanding)

Go deeper — visual, from zero

Test yourself — CMOS Circuit Design

Connections