Pull-up and pull-down networks: Foundations — Hardware deep dive

We must earn every symbol the parent note throws at you. We build them in strict order — each one leans only on the ones before it — and we do not use the words "pull-up network" or "pull-down network" as technical objects until §8, where we define them from the parts already built.

1. Voltage $V$ , and the output voltage $V_{o u t}$

Why the topic needs it: a logic gate must move its output voltage $V_{o u t}$ to one of two clearly different heights — one we call "logic 1", one we call "logic 0". Everything else exists to control $V_{o u t}$ .

2. The rails: $V_{D D}$ and ground ( $0 V$ )

Why the topic needs it: "pull up" will mean "connect $V_{o u t}$ to the $V_{D D}$ line"; "pull down" will mean "connect $V_{o u t}$ to the $0 V$ line". The two rails ARE up and down.

3. Logic levels: what `1` and `0` really are

Why the topic needs it: the entire justification for using two kinds of transistor is to keep both levels clean instead of degraded.

4. The transistor as a switch

The parent note names two devices — NMOS and PMOS. Let us define a transistor as gently as possible.

5. $V_{GS}$ , $V_{S G}$ — the gate-to-source voltage

Why two versions ( $V_{GS}$ and $V_{S G}$ )? Because the two transistor types turn on for opposite comparisons — one wants the gate above its source, the other wants the gate below. We need both subtractions ready.

6. Threshold voltage: $V_{t n}$ , $V_{tp}$ , and the bars $∣ \cdot ∣$

The figure below plots the NMOS case; the PMOS case is its mirror image (a rising floor at $∣ V_{tp} ∣$ instead of a falling ceiling at $V_{D D} - V_{t n}$ ).

7. Series and parallel — why AND/OR must follow

This is not merely an analogy — the Boolean meaning is forced by one physical fact: a switch has no partial state. It is either fully closed (call it 1) or fully open (0); there is no "half-open". Let $c_{1}, c_{2}$ be the closed/open state of two switches. Then:

8. Building the two networks and why they must be complements

Now, and only now, we name the two teams — and we derive the golden rule instead of asserting it.

Now derive the rule by exhausting all four possible team states:

Formula Why the networks MUST be perfect complements

The output wire can be connected to $V_{D D}$ (via PUN) and/or to $0 V$ (via PDN). Four cases:

$g_{P U N}$	$g_{P D N}$	what happens to $V_{o u t}$
1	1	$V_{D D}$ shorted to $0 V$ through the output — huge current, output stuck at a useless middle voltage. Forbidden.
0	0	output connected to nothing — it floats, holding no defined level. Forbidden.
1	0	output tied only to $V_{D D}$ ⇒ clean `1` ⇒ $Y = 1$ . ✔
0	1	output tied only to $0 V$ ⇒ clean `0` ⇒ $Y = 0$ . ✔

Only the last two rows are legal, and in both $g_{P D N}$ is the opposite of $g_{P U N}$ . Therefore a correct gate requires $g_{P D N} = \overline{g_{P U N}} (exactly one network conducts — never both, never neither) .$ And reading off the two legal rows, the output digit is $Y = \overline{g_{P D N}} (high precisely when the pull-down is OFF).$

Because $g_{P D N}$ and $g_{P U N}$ are built from series/parallel switches, and series/parallel are AND/OR (§7), forcing them to be complements is exactly De Morgan's Theorem: $\overline{A \cdot B} = \overline{A} + \overline{B}, \overline{A + B} = \overline{A} \cdot \overline{B}$ Swapping series ↔ parallel between the PDN and PUN is applying the bar — which is why the dual construction in the parent note automatically satisfies $g_{P D N} = \overline{g_{P U N}}$ . See it in action in CMOS Inverter and NAND and NOR gates (and the related device style Pass Transistor Logic).

9. Two power edge-cases: static (steady) and short-circuit (switching)

Equipment checklist

Cover the right side and answer each before moving to the next child page.

What does voltage measure, and what is

V_{o u t}

Voltage is electrical "push" (height) in volts;

V_{o u t}

is the voltage on the gate's output wire.

What are the two fixed rails in a CMOS gate?

V_{D D}

(fixed high) and ground

0 V

(fixed low).

What is a "rail-to-rail" (clean) logic level vs a degraded one?

Clean sits exactly on a rail (

V_{D D}

0 V

); degraded falls short and risks misreading.

What are a transistor's three terminals and what does the gate do?

Gate (control knob, draws no current), source and drain (the switch contact); gate voltage opens/closes it.

What does

V_{GS}

mean and why a difference?

V_{G} - V_{S}

; a switch reacts to gate relative to its source, not absolute height.

When does an NMOS turn ON? A PMOS?

NMOS when

V_{GS} > V_{t n}

; PMOS when

V_{S G} > ∣ V_{tp} ∣

Which level does NMOS degrade, and which does PMOS degrade?

NMOS degrades a 1 (caps at

V_{D D} - V_{t n}

); PMOS degrades a 0 (caps at

∣ V_{tp} ∣

Series switches implement which Boolean op? Parallel? And why is it forced?

Series = AND, parallel = OR; because a switch has no partial state, "conducting?" equals

c_{1} \cdot c_{2}

(series) or

c_{1} + c_{2}

(parallel).

What are the PUN and PDN made of, and to which rail does each connect?

PUN of PMOS to

V_{D D}

; PDN of NMOS to

0 V

Why must

g_{P D N} = \overline{g_{P U N}}

Both-on shorts the rails; both-off floats the output; only the two complementary rows give a clean, defined level.

How does the Boolean

Y

relate to the physical

V_{o u t}

Y

is the logic digit read off

V_{o u t}

Y = 1

when

V_{o u t}

is a clean 1,

Y = 0

when a clean 0.

Why is there no static power in a correct static CMOS gate?

The complementary rule forbids a steady

V_{D D}

-to-

0 V

path.

When does current still flow from

V_{D D}

to ground, despite complementarity?

Briefly during an input transition — short-circuit (dynamic) current while both networks momentarily conduct.