Pull-up and pull-down networks: Worked examples — Hardware deep dive

This page is the drill-ground for Pull-up and pull-down networks. The parent taught the rules; here we exercise them against every kind of case a gate can throw at you — simple, degenerate, compound, and exam-twisted. Guess before you read the steps.

The scenario matrix

Before any example, here is the full grid of case-classes this topic can present. Every cell is covered by at least one worked example below.

Cell	Case class	What makes it tricky	Covered by
C1	Single input (degenerate)	one transistor per network — no series/parallel choice	Ex 1
C2	Pure AND-term (series PDN)	series↔parallel flip must be applied	Ex 2
C3	Pure OR-term (parallel PDN)	the mirror of C2	Ex 3
C4	Mixed AND-of-OR / OR-of-AND (compound AOI/OAI)	nesting series inside parallel and vice-versa	Ex 4, Ex 5
C5	Non-inverting target (AND / OR gate)	static CMOS can only invert → needs an extra inverter stage	Ex 6
C6	Degenerate / illegal design	series↔series copy shorts the rails or floats output	Ex 7
C7	Limiting/electrical case	threshold drop, series stacking slows things — the analog limit	Ex 8
C8	Real-world word problem	translate English → Boolean → transistors	Ex 9
C9	Exam twist (count transistors / recognise a mystery gate)	reverse-engineer the function from a netlist	Ex 10

Ex 1 — Inverter (Cell C1: single input, degenerate)

Forecast: guess the transistor count and which type sits on top before reading on.

Read $f$ . $Y = \overline{f}$ so $f = A$ . Why this step? The PDN must conduct when $f = 1$ , i.e. when $A = 1$ .
PDN. One NMOS, gate $= A$ , between $Y$ and ground. Why? A single variable needs a single switch — no AND/OR, so no series/parallel to decide.
PUN (dual of one device = one device). One PMOS, gate $= A$ , between $V_{D D}$ and $Y$ . Why? A PMOS conducts when its gate is low, so at $A = 0$ it pulls $Y$ high — exactly the complement.

Figure 1 (below): the PMOS (red, the key pull-up device) sits on top tied to $V_{D D}$ ; the black NMOS sits below tied to ground; the output node $Y$ is the shared wire between them. Notice both devices share the same gate label $A$ .

Verify: $A = 0 \Rightarrow$ PMOS ON, NMOS OFF $\Rightarrow Y = 1$ . $A = 1 \Rightarrow$ NMOS ON, PMOS OFF $\Rightarrow Y = 0$ . Exactly one network conducts per input. Total transistors $= 2$ . ✔ (See CMOS Inverter — the single-input base case whose sizing sets the switching threshold.)

Ex 2 — 2-input NAND (Cell C2: series PDN)

Forecast: series or parallel in the PDN? And in the PUN?

Read $f = A \cdot B$ . Why? Output goes low only when both $A$ AND $B$ are 1.
PDN = two NMOS in series (gates $A$ , $B$ ). Why? Series = AND: current reaches ground only if both switches are closed.
PUN = dual = two PMOS in parallel (gates $A$ , $B$ ), written PMOS $A ∥$ PMOS $B$ . Why? Series↔parallel flip. Boolean check: $\overline{A \cdot B} = \overset{ˉ}{A} + \overset{ˉ}{B}$ , so output is high if either input is low → each PMOS can pull up alone → parallel.

Figure 2 (below): the two red PMOS on top are wired between the same two nodes ( $V_{D D}$ and $Y$ ) — that side-by-side wiring is what "parallel" looks like. Below, the two black NMOS are stacked end-to-end (series) between $Y$ and ground.

Verify: at $A = B = 1$ : series NMOS conducts $\Rightarrow Y = 0$ , both PMOS OFF. Every other row: at least one input is 0 $\Rightarrow$ that PMOS ON $\Rightarrow Y = 1$ , series NMOS broken. Truth table matches NAND. ✔ (See NAND and NOR gates — NAND is the universal gate every other function can be built from; and De Morgan's Theorem, which is exactly the algebra that turns the series AND into the parallel OR here.)

Ex 3 — 2-input NOR (Cell C3: parallel PDN)

Forecast: this is the mirror of Ex 2 — predict both networks.

Read $f = A + B$ . Why? Output goes low when $A$ OR $B$ is 1.
PDN = two NMOS in parallel, i.e. NMOS $A ∥$ NMOS $B$ . Why? Parallel = OR: either switch alone completes a path to ground.
PUN = dual = two PMOS in series. Why? We flip parallel→series (the dual rule). Boolean confirmation: $\overline{A + B} = \overset{ˉ}{A} \cdot \overset{ˉ}{B}$ , so output is high only when both inputs are low → both PMOS must conduct → series.

Verify: at $A = B = 0$ : series PMOS conducts $\Rightarrow Y = 1$ , both NMOS OFF. Any input high: that NMOS ON $\Rightarrow Y = 0$ . Matches NOR truth table. ✔ (Compare with NAND and NOR gates: NOR is NAND's structural mirror image.)

Ex 4 — AOI compound gate (Cell C4: OR-of-AND nesting)

Forecast: guess where $C$ sits relative to the $A, B$ pair — series or parallel?

Read $f = (A \cdot B) + C$ . Why? This tells us the PDN structure directly.
PDN. $A \cdot B$ ⇒ NMOS $A$ in series with NMOS $B$ ; that whole branch in parallel with NMOS $C$ . Why? Inner AND → series; outer OR → parallel.
PUN (dual). Flip every connection: OR→series, AND→parallel. So PMOS $C$ in series with the group (PMOS $A ∥$ PMOS $B$ ). Why? Duality maps the outer OR to a series link and the inner AND to a parallel pair.

Figure 3 (below): in the PDN the red $A$ – $B$ pair is stacked (series) and that stack sits alongside the lone $C$ device (parallel) — read the shape straight off the picture: stacked = AND, side-by-side = OR.

Verify: transistor count $= 3$ NMOS $+ 3$ PMOS $= 6$ . Force $Y = 0$ : need $f = 1$ , e.g. $A = B = 1$ (series branch conducts) OR $C = 1$ . Force $Y = 1$ : e.g. $C = 0$ and ( $A = 0$ or $B = 0$ ) → PMOS $C$ ON and one of the parallel PMOS ON → full series path from $V_{D D}$ . Complementary for all 8 rows. ✔

Ex 5 — OAI compound gate (Cell C4: AND-of-OR nesting)

Forecast: this is Ex 4 with AND/OR swapped — predict the PDN before reading.

Read $f = (A + B) \cdot C$ . Why? Output low when ( $A$ OR $B$ ) AND $C$ both true.
PDN. $A + B$ ⇒ NMOS $A ∥$ NMOS $B$ ; that group in series with NMOS $C$ . Why? Inner OR → parallel; outer AND → series.
PUN (dual). AND→parallel, OR→series: (PMOS $A$ series PMOS $B$ ) in parallel with PMOS $C$ . Why? Flip both levels of nesting.

Verify: $Y = 0$ needs $C = 1$ and ( $A = 1$ or $B = 1$ ). Set $A = 1, C = 1$ : parallel NMOS branch + series NMOS $C$ conduct → $Y = 0$ ; on the PUN side PMOS $C$ (gate 1) OFF and the series $A, B$ path broken by $A = 1$ → PUN OFF. Complementary. ✔

Ex 6 — Building an AND gate (Cell C5: non-inverting target)

Forecast: yes or no? And if no, what's the fix?

Recognise the constraint. A static CMOS gate can only compute $Y = \overline{f}$ — it is inherently inverting. Why? The PDN pulls down when $f = 1$ ; there's no way for a pull-down to raise the output, so the output is always the complement of "PDN conducts".
Nearest single stage. Build $\overline{A \cdot B}$ (the NAND from Ex 2). Why? It's the closest inverting relative of AND.
Add an inverter. Feed NAND's output through an inverter (Ex 1): $\overline{\overline{A \cdot B}} = A \cdot B$ . Why? Two inversions cancel, restoring the non-inverting AND.

Verify: transistor count $= 4$ (NAND) $+ 2$ (inverter) $= 6$ . Truth table: only $A = B = 1$ gives $Y = 1$ . Matches AND. ✔ (Same trick makes OR $=$ NOR $+$ inverter; the added stage is exactly the CMOS Inverter.)

Ex 7 — The illegal "copy the PDN" design (Cell C6: degenerate)

Forecast: does it short the rails, float the output, or work fine?

Write both conduction conditions. PDN (series NMOS): conducts when $A \cdot B = 1$ , i.e. $g_{P D N} = A \cdot B$ . PUN (series PMOS): conducts when $\overset{ˉ}{A} \cdot \overset{ˉ}{B} = 1$ , i.e. $g_{P U N} = \overset{ˉ}{A} \cdot \overset{ˉ}{B}$ (needs $A = B = 0$ ). Why? Series PMOS needs both gates low. (Recall $g_{P D N}$ / $g_{P U N}$ from the definition box: they are 1 when that network has a closed path.)
Test the golden rule $g_{P D N} = \overline{g_{P U N}}$ — "PDN conducts exactly when the PUN does not". At $A = 1, B = 0$ : $g_{P D N} = 1 \cdot 0 = 0$ (PDN off) and $g_{P U N} = 0 \cdot 1 = 0$ (PUN off). Neither conducts → output floats. Why bad? A floating node holds no defined logic level and leaks.
Correct it. The PUN must be the dual: two PMOS in parallel (PMOS $A ∥$ PMOS $B$ ), which conducts when $\overset{ˉ}{A} + \overset{ˉ}{B} = 1$ — the exact complement of $A \cdot B$ . Why? Only the dual makes $g_{P D N} = \overline{g_{P U N}}$ hold, guaranteeing "exactly one network conducts, always".

Figure 4 (below): the red output node $Y$ is drawn dangling — for $A = 1, B = 0$ neither the top (series PMOS) nor bottom (series NMOS) has a complete path, so nothing drives $Y$ .

Verify: wrong design leaves ${A, B} = {1, 0}$ and ${0, 1}$ floating (2 of 4 rows broken). The dual (parallel PMOS) covers all four rows with exactly-one-conducts. ✔

Ex 8 — Series stacking, the electrical limit (Cell C7: limiting case)

Forecast: guess whether wide stacks get faster or slower.

Count. 4-input NAND: PDN $= 4$ NMOS series, PUN $= 4$ PMOS parallel $\Rightarrow 8$ transistors. Why? One NMOS + one PMOS per input, always.
Series resistance adds. Four ON-NMOS in series have roughly $4 \times$ the single-device resistance, so pulling $Y$ low is slower. Why? Series resistors sum; the RC discharge time grows. (Related: Threshold Voltage and Body Effect — a stacked device sits above ground, so body effect raises its $V_{t n}$ , making it weaker still.)
Limiting behaviour. As stack height $\to$ large, delay grows roughly linearly, which is why real designs cap fan-in (typically $\leq 4$ ) and split wide functions across stages. Why? Beyond that the AOI advantage is lost to sluggish series paths.

Verify: transistor count for $n$ -input NAND $= 2 n$ ; at $n = 4$ that is $8$ . Pull-down resistance scales as $\approx n \cdot R_{o n}$ ; at $n = 4$ it is $\approx 4 R_{o n}$ . ✔ (This resistance-vs-speed trade feeds directly into Static vs Dynamic Power, which separates leakage from switching energy.)

Ex 9 — Word problem: a safety interlock (Cell C8: real-world)

Forecast: what's $f$ (the pull-down condition)?

English → Boolean. Lamp on: $Y = A + (B \cdot C)$ . Why? "OR" between the guard term and the " $B$ AND $C$ " term.
It's non-inverting (like Ex 6), so build the inverting core $\overline{A + B \cdot C}$ first, then invert. Why? Static CMOS gives $\overline{f}$ ; here $f = A + B \cdot C$ .
PDN of the core. NMOS $A ∥$ (NMOS $B$ series NMOS $C$ ). Why? Outer OR → parallel; inner AND → series. PUN (dual): PMOS $A$ in series with (PMOS $B ∥$ PMOS $C$ ).
Add an inverter so the final lamp signal is $\overline{\overline{A + B C}} = A + B C$ . Why? We wanted the non-inverted meaning.

Verify: core has $3$ NMOS + $3$ PMOS $= 6$ , plus $2$ for the inverter $= 8$ . Check $A = 0, B = 1, C = 1$ : series NMOS $B C$ conducts → core output $= 0$ → after inverter $Y = 1$ (lamp ON). $A = 0, B = 1, C = 0$ : neither PDN branch complete → core $= 1$ → $Y = 0$ (lamp off). Matches spec. ✔

Ex 10 — Reverse-engineer a mystery netlist (Cell C9: exam twist)

Forecast: guess $Y$ before working the algebra.

Translate the PDN to $f$ . Series $A$ with (parallel $B, C$ ) $\Rightarrow f = A \cdot (B + C)$ . Why? Series = AND, parallel = OR — read the topology straight off.
Apply the inversion. $Y = \overline{f} = \overline{A \cdot (B + C)}$ . Why? Every static CMOS stage outputs $\overline{f}$ .
Sanity via De Morgan (predicts PUN). $\overline{A \cdot (B + C)} = \overset{ˉ}{A} + \overline{B + C} = \overset{ˉ}{A} + \overset{ˉ}{B} \overset{ˉ}{C}$ . So the PUN is PMOS $A ∥$ (PMOS $B$ series PMOS $C$ ) — dual of the PDN, as expected. Why? Confirms the design is complementary. (This is De Morgan's Theorem doing the topology flip for us.)

Verify: transistor count $= 3$ NMOS $+ 3$ PMOS $= 6$ . Truth check: $Y = 0$ only when $A = 1$ and ( $B = 1$ or $C = 1$ ). E.g. $A = 1, B = 0, C = 0 \Rightarrow f = 0 \Rightarrow Y = 1$ ; $A = 1, C = 1 \Rightarrow f = 1 \Rightarrow Y = 0$ . Consistent with $Y = \overline{A (B + C)}$ . ✔

Active Recall

Recall Did every matrix cell get covered?

Single input (C1) ::: Ex 1 Series PDN / pure AND (C2) ::: Ex 2 Parallel PDN / pure OR (C3) ::: Ex 3 Compound AOI and OAI (C4) ::: Ex 4, Ex 5 Non-inverting target needing extra inverter (C5) ::: Ex 6, Ex 9 Illegal same-topology design (C6) ::: Ex 7 Electrical limiting case / series stacking (C7) ::: Ex 8 Real-world word problem (C8) ::: Ex 9 Exam reverse-engineering twist (C9) ::: Ex 10