Exercises — Pull-up and pull-down networks

L1.1 The PUN is built from PMOS transistors and connects the output to ==$V_{DD}$== (the logic-1 rail). Why PMOS up top: a PMOS passes a strong 1 (no threshold drop when pulling toward $V_{DD}$), so it restores a clean HIGH. See CMOS Inverter.

L1.2 Series = AND. Current only flows if both NMOS are ON, i.e. input $A$ AND input $B$ are both 1. (Mnemonic SAPO: Series-AND, Parallel-OR.)

L1.3 $g_{PDN}=\overline{g_{PUN}}$ — the two networks are logical complements: never both conduct (that would short $V_{DD}$ to ground), never neither (that would leave the output floating).

L2.1 — 3-input NAND. Here $f=A\cdot B\cdot C$ and $Y=\bar{f}$.

• PDN: output must go LOW only when $A\cdot B\cdot C=1$ ⇒ we need all three NMOS ON ⇒ AND ⇒ three NMOS in series (gates $A,B,C$) between $Y$ and ground.
• PUN (dual): swap series→parallel ⇒ three PMOS in parallel (gates $A,B,C$) between $V_{DD}$ and $Y$. This matches De Morgan: $\overline{ABC}=\bar{A}+\bar{B}+\bar{C}$, so the output is HIGH if any input is low — exactly "any parallel PMOS turns on."
• Check $A=B=C=1$: the series NMOS chain is a complete wire → $Y=0$. Every PMOS has gate 1 → all OFF. Exactly one network conducts. ✔
• Check $A=1,B=1,C=0$: NMOS chain broken (the $C$ switch is open) → PDN OFF. PMOS with gate $C=0$ is ON → PUN pulls $Y=1$. ✔ ($Y=\overline{1\cdot 1\cdot 0}=\overline{0}=1$.)

L2.2 — 3-input NOR. $f=A+B+C$.

• PDN: LOW when any input is 1 ⇒ OR ⇒ three NMOS in parallel.
• PUN (dual): parallel→series ⇒ three PMOS in series. Output is HIGH only when all inputs are 0 (all series PMOS ON) — matches $\overline{A+B+C}=\bar{A}\bar{B}\bar{C}$. See NAND and NOR gates.

L2.3 Each gate uses $2n=6$ transistors: one NMOS and one PMOS per input. Every input drives exactly one NMOS (in the PDN) and exactly one PMOS (in the PUN), because the PUN is the dual of the PDN with the same set of inputs. So $n$ inputs → $n$ NMOS + $n$ PMOS $=2n$.

L3.1 Trace current from $Y$ to ground. First it must pass through $A$ (series) — that's an AND with whatever follows. After $A$, the current can go through $B$ or $C$ (parallel) — that's an OR. So the PDN conducts when $f=A\cdot (B+C).$ The output is the inversion: $Y=\overline{f}=\overline{A(B+C)}$.

L3.2 Dualise branch by branch:

• $A$ in series with the rest (PDN) → $A$ in parallel with the rest (PUN).
• The parallel pair $(B\parallel C)$ (PDN) → series pair $(B$–$C)$ (PUN).

So the PUN = PMOS $A$ in parallel with [PMOS $B$ in series with PMOS $C$]. Confirm by De Morgan: $Y=\overline{A(B+C)}=\bar{A}+\overline{(B+C)}=\bar{A}+\bar{B}\bar{C}$. Read the PUN: it conducts (pulls HIGH) when $A=0$ OR when $B=0$ and $C=0$ — i.e. $\bar{A}+\bar{B}\bar{C}$. Identical. ✔

L3.3 In the figure the PDN is a series pair (A then B) in parallel with a single NMOS C. So it conducts when $(A\cdot B)+C=1$, giving $Y=\overline{(A\cdot B)+C}.$ Inside the bar we do AND then OR then invert → this is an AOI (AND-OR-Invert) gate.

L4.1 $f=A+B\cdot C$.

• PDN: the OR ($A+\dots$) → parallel; the AND ($B\cdot C$) → series. So: NMOS $A$ in parallel with (NMOS $B$ in series with NMOS $C$).
• PUN (dual): OR→series, AND→parallel: PMOS $A$ in series with (PMOS $B$ ∥ PMOS $C$). Check via De Morgan: $Y=\overline{A+BC}=\bar{A}\cdot \overline{BC}=\bar{A}(\bar{B}+\bar{C})$ — pulls HIGH when $A=0$ AND ($B=0$ OR $C=0$): $A$ in series (the AND) with the $B\parallel C$ pair (the OR). ✔
• Transistors: 3 inputs ⇒ 3 NMOS + 3 PMOS = 6.

L4.2 $f=(A+B)\cdot (C+D)$.

• PDN: outer AND → series of two branches; each inner OR → parallel pair. So: (NMOS $A$ ∥ NMOS $B$) in series with (NMOS $C$ ∥ NMOS $D$).
• PUN (dual): swap everything: (PMOS $A$ series PMOS $B$) in parallel with (PMOS $C$ series PMOS $D$). Check: $Y=\overline{(A+B)(C+D)}=\overline{A+B}+\overline{C+D}=\bar{A}\bar{B}+\bar{C}\bar{D}$ — HIGH when ($A,B$ both 0) OR ($C,D$ both 0) → two series PMOS branches in parallel. ✔ 4 inputs ⇒ 8 transistors.

L4.3 No — not as a single static-CMOS gate. Every static-CMOS gate is inherently inverting ($Y=\overline{f}$), because the PDN can only pull down and the PUN only up, and they are complements. A bare AND is non-inverting. Smallest correct realisation: a NAND ($Y^{\prime }=\overline{AB}$, 4 transistors) followed by an inverter ($Y=\overline{Y^{\prime }}=AB$, 2 transistors) = 6 transistors. The inverter restores the missing inversion. (A Pass Transistor Logic AND can be smaller but doesn't give full rail-to-rail restoration.)

L5.1 Series resistances add: three NMOS in series give worst-case pull-down resistance $R_{PDN}=R+R+R=3R.$ Three PMOS in parallel give conductances that add; the best case (any one ON, but if all three are ON) is $R_{PUN}=\frac{R_p}{3}.$ The series stack ($3R$) is large and it charges/discharges the output slowly ⇒ it sets the slow (falling) edge. That's why designers make series-stacked transistors wider (lower $R$) to compensate — and why deep series stacks are avoided. (Threshold and body effect, from Threshold Voltage and Body Effect, make stacked devices even weaker, worsening this.)

L5.2 Ideal steady-state DC current $=0$. Why: by the golden rule exactly one network conducts at a time, so there is never a complete wire from $V_{DD}$ to ground while inputs are stable — no static path, hence (ideally) no static power. Current flows only during switching, when the input crosses the threshold and both networks are briefly partly-ON (short-circuit current) plus the current charging the load capacitance — this is dynamic power. See Static vs Dynamic Power.

L5.3 With $C=1$: the $C$-NMOS in the PDN is permanently ON, so the PDN conducts regardless of $A,B$ ⇒ output is dragged LOW always ⇒ $Y=\overline{(A\cdot B)+1}=\overline{1}=0.$ The output is a constant 0. The $A$ and $B$ transistors (both PDN NMOS and the PUN PMOS $A\parallel B$) become don't-care — their inputs no longer affect $Y$. (In the PUN, $C=1$ turns the series PMOS $C$ OFF, guaranteeing the PUN cannot pull HIGH — consistent.)