Question bank — Pull-up and pull-down networks

False. By the golden rule $g_{PDN}=\overline{g_{PUN}}$, exactly one network conducts for every input — both conducting would short $V_{DD}$ straight to ground and burn huge current.

False in a correctly designed static gate. If both were OFF the output would float (no path to either rail), holding an undefined, drifting voltage — a design bug, not a valid state.

False. It stops once $V_{GS}$ falls to $V_{tn}$, so the output caps at $V_{DD}-V_{tn}$ — a degraded 1. That is exactly why NMOS lives in the pull-down network.

False. PMOS stops sinking once $V_{SG}$ drops to $|V_{tp}|$, so it caps a LOW at $|V_{tp}|$ — a degraded 0. It passes a strong 1, hence it belongs in the pull-up network.

True. Current gets through only when both transistors are ON, i.e. both gate inputs are 1 — that conjunction is exactly AND.

False. The PUN is the dual: series↔parallel are swapped. Copying the topology produces a gate that either shorts the rails or floats the output for some inputs.

False. A single static CMOS stage is inherently inverting: $Y=\overline{f}$. You get AND only by following NAND with an inverter — never in one stage.

False. PMOS turns ON when its gate is pulled low ($V_{SG}>|V_{tp}|$). The built-in "bubble" is precisely why a PMOS with input $A$ realises the $\bar{A}$ term of the pull-up.

False. NMOS cannot restore a clean 1, so the output sags to $V_{DD}-V_{tn}$, cutting noise margin and leaking static current into the next stage — see the parent's steel-man.

False. NAND has $f=A\cdot B$ (AND), and AND maps to series NMOS. Parallel NMOS is the NOR case ($f=A+B$).

Wrong — NOR's $f=A+B$ is an OR, which maps to parallel NMOS. Series would only pull low when both are 1, giving an AND-like PDN.

Wrong — that mirrors instead of dualises. Series-PDN must become parallel-PUN; two series PMOS only pull high when both inputs are 0, which floats the output for the $A\ne B$ cases.

Wrong transistor. NMOS degrades the HIGH to $V_{DD}-V_{tn}$; the pull-up must use PMOS so the output reaches a full $V_{DD}$.

Not fine for a static combinational gate. A floating node drifts with leakage and noise; static CMOS demands a driven path to a rail for every input. (Deliberate floating belongs to Pass Transistor Logic/dynamic logic, not here.)

The PDN is right but the PUN is wrong — the dual of series is parallel. Correct PUN: PMOS $A$ ∥ PMOS $B$.

The right-hand side is an OR of the complements, and OR maps to parallel PMOS — the bubbles (low-active PMOS) already supply the $\bar{A},\bar{B}$; you only wire the OR as parallel.

Backwards. $Y=\overline{g_{PDN}}$: the output is HIGH exactly when the PDN is OFF (and the PUN is ON pulling it up).

No single transistor type restores both rails cleanly — NMOS gives a strong 0 but weak 1, PMOS a strong 1 but weak 0. Two complementary networks put each device where it excels, yielding rail-to-rail output.

Series encodes AND and parallel encodes OR; De Morgan says $\overline{A\cdot B}=\bar{A}+\bar{B}$ and $\overline{A+B}=\bar{A}\cdot \bar{B}$, so swapping series/parallel is applying De Morgan's Theorem, which flips the conduction condition to the complement.

Because exactly one network conducts at a time, there is never a continuous conducting path from $V_{DD}$ to ground once the output settles — no DC current, so no static power (only leakage remains).

PMOS is low-active: input $A=0$ turns the PMOS ON while the same $A=0$ turns the matching NMOS OFF. The complement is built into the device polarity, so both are driven by the raw $A$.

A static CMOS stage can realise any single inverting AND-OR (or OR-AND) function in one gate, so you avoid extra inverting stages — fewer transistors, less delay, and only one inversion.

Series conduction pulls the output toward ground, and NMOS passes a strong 0 all the way to $0V$; using PMOS there would cap the LOW at $|V_{tp}|$, a degraded zero.

PMOS is fully ON ($V_{SG}=V_{DD}>|V_{tp}|$) and NMOS is fully OFF, so the output is pulled cleanly to $V_{DD}$ — a rail-to-rail 1. See CMOS Inverter.

The series NMOS chain is broken (B off), so PDN is OFF; PMOS $B$ is ON (its input is 0), so the parallel PUN pulls the output to 1. Any single low input suffices.

That one NMOS (in parallel) conducts and pulls the output LOW; the series PMOS chain is broken, so PUN is OFF. Output 0 whenever any input is 1.

There can be a brief window where both networks partially conduct, causing a short-lived dynamic current spike (short-circuit current) — this is dynamic power, distinct from static power, and it vanishes once the input settles.

$f=(AB)+C=1$, so the PDN conducts (the parallel $C$-NMOS pulls low) and $Y=0$ — the single $C$ transistor alone forces the output low.

When $f=A+BC=0$, i.e. $A=0$ and ($B=0$ or $C=0$). Then the PDN is fully OFF and the PUN pulls the output to 1.

$V_{tn}$ itself increases with source-to-body voltage (body effect), so the cap $V_{DD}-V_{tn}$ gets even lower — the degraded 1 is worse than the naive estimate. This is why NMOS pull-ups are avoided; details in Threshold Voltage and Body Effect.