Pull-up and pull-down networks: Visual walkthrough

We derive the central result: $Y = \overline{f (inputs)}, g_{P D N} = \overline{g_{P U N}}$ from zero. Every symbol below is earned before it is used.

Step 1 — A wire that must become HIGH or LOW

WHAT: we place the output wire between two rails. WHY: a gate's whole job is to decide whether $Y$ ends up touching the top rail or the bottom rail — nothing in between is a valid logic level. PICTURE: the bucket. Filling it to the brim = logic 1; emptying it to the floor = logic 0.

Step 2 — A single switch: the transistor

WHAT: we introduce the only building block — a switch controlled by an input. WHY: we cannot move charge onto or off the wire without something that opens and closes a path. That "something" is the transistor. PICTURE: two switch symbols side by side — NMOS closes when you push its knob up, PMOS closes when you push its knob down. See the CMOS Inverter for these two working as a pair.

Step 3 — WHY the strong switch goes on the correct side

WHAT: we show that an NMOS cannot finish the job of charging $Y$ to the very top. WHY: this single fact forces the whole architecture. NMOS is only trustworthy pulling down to $0$ (there the source stays at GND, the knob stays fully pressed). Symmetrically, PMOS stalls at $∣ V_{tp} ∣$ when pulling low, so PMOS is only trustworthy pulling up. PICTURE: two voltage-vs-time curves. The red NMOS-pull-up curve flattens early at $V_{D D} - V_{t n}$ ; the green NMOS-pull-down curve reaches $0$ cleanly.

Step 4 — Two teams, and the golden rule

WHAT: we require the two teams to be perfect opposites. WHY: two failure modes must be banned for every input:

If both conducted → a wire straight from $V_{D D}$ to GND → a short circuit burning huge current (kills static power budget).

If neither conducted → $Y$ floats, holding no defined logic level → garbage output.

The only safe design is "exactly one team on, always". That is $g_{P D N} = \overline{g_{P U N}}$ . PICTURE: a 2×2 truth grid of (PUN on/off) × (PDN on/off). Two cells are red-forbidden (both/neither), the diagonal two are green-legal.

Step 5 — Series means AND, parallel means OR

WHAT: we translate wiring shape into Boolean algebra. WHY: the gate must pull $Y$ LOW exactly when the target function $f = 1$ . If we can build any $f$ out of series/parallel switches, we can realise any gate. Series and parallel are the two atoms — everything else nests these. PICTURE: left, two switches in a line with a single water pipe that flows only if both open (AND). Right, two switches on separate pipes, flow if either opens (OR).

Step 6 — The PUN is the DUAL (De Morgan, drawn)

WHAT: we generate the top network by flipping the bottom one's shape. WHY: flipping series↔parallel is literally applying De Morgan, which is exactly the complement we required in Step 4. No extra thinking needed — the geometry does the algebra. PICTURE: a mirror. Bottom: NMOS $A$ – $B$ in series → top mirror-image: PMOS $A$ – $B$ in parallel. The overbar "bubble" of each PMOS supplies the $\overset{ˉ}{A}$ .

Step 7 — The full result, checked on NAND

WHAT: we verify the derived machine on a real gate. WHY: a derivation is only trustworthy if it survives every input combination — including the corner where both inputs are 1 and the degenerate where an input is 0. PICTURE: the NAND schematic with a small truth table; each row coloured by which team is ON. Compare with NAND and NOR gates.

Step 8 — The degenerate case: what if we ignore the dual?

WHAT: we deliberately break the rule to see the failure. WHY: the reader must never trust a shortcut; showing the exact input that floats proves the dual is not optional. PICTURE: the mis-wired NAND with input $A = 1, B = 0$ , $Y$ drawn dangling with a red "?" — no path up, no path down.

The one-picture summary

This single diagram is the whole derivation: pick $f$ → NMOS PDN by SAPO → mirror to PMOS PUN → exactly one team conducts per input → $Y = \overline{f}$ , rail-to-rail, zero static current. (This is also why Pass Transistor Logic, which uses lone transistors, suffers the degraded-level problems Step 3 warned about.)

Recall Feynman retelling — the whole walk in plain words

We started with one wire that has to be either all-the-way-full (1) or all-the-way-empty (0). Our only tool is a switch you flip with an input. But we discovered switches are one-trick: the "drain" switch (NMOS) empties the wire perfectly but can't fill it to the brim — it quits early. The "filler" switch (PMOS) fills perfectly but can't empty fully. So we hire two teams: fillers up top, drainers down below. The one unbreakable rule is exactly one team works at a time — if both worked we'd pour water from tap to drain forever (short, wasted power); if neither worked the bucket would just sit at some random level (float, garbage). To build the drainers we use a simple code: switches in a row mean "AND" (all must open), switches side by side mean "OR" (any opens) — that's how we make the bucket empty for any logic rule we want. Then, to get the fillers, we don't think again — we just mirror the wiring: rows become side-by-sides and vice versa. That mirror trick is secretly De Morgan's law, and it's what forces the two teams to be perfect opposites. We tested it on a NAND across all four inputs, then deliberately mis-wired it to watch the output float — proving the mirror step is mandatory. That's a CMOS gate, from one wire to a working machine.

Recall Self-check

Why must a series-PDN become a parallel-PUN? ::: Because $\overline{A \cdot B} = \overset{ˉ}{A} + \overset{ˉ}{B}$ ; swapping series↔parallel applies De Morgan, giving the required complement $g_{P U N} = \overline{g_{P D N}}$ . What two forbidden situations does the golden rule ban? ::: Both networks on (short $V_{D D}$ →GND) and neither on ( $Y$ floats). Where does the NMOS stall when pulling up, and why does that force PMOS on top? ::: At $V_{D D} - V_{t n}$ , because its own rising source cuts $V_{GS}$ to $V_{t n}$ ; PMOS has no such HIGH ceiling.