Dynamic CMOS logic

WHAT it is

The gate structure:

1 PMOS (Mp) gated by clock $\phi$ → precharge.
PDN of NMOS transistors implementing the logic function.
1 NMOS (Me, the evaluation/foot transistor) gated by $\phi$ → prevents discharge during precharge.

WHY it works — derive the two phases from first principles

The output node is just a capacitor $C_L$ (gate caps of the next stage + wire + drain caps). Its voltage obeys charge conservation: $Q = C_L \, V_{out}, \qquad I = C_L \frac{dV_{out}}{dt}.$

Precharge ( $\phi=0$ ):

$Mp$ (PMOS) sees gate $=0$ , so $V_{GS}=0-V_{DD}=-V_{DD}<V_{tp}$ → ON. It pulls $V_{out}\to V_{DD}$ .
$Me$ (foot NMOS) sees gate $=0$ → OFF. So even if the PDN wants to conduct, there is no path to ground — no fight between pull-up and pull-down (unlike static CMOS which never has both on).

Evaluate ( $\phi=1$ ):

$Mp$ off (gate $=V_{DD}$ ), $Me$ on (gate $=V_{DD}$ ).
If the PDN inputs form a conducting path, charge drains: $V_{out}: V_{DD}\to 0$ (logic 0).
If the PDN is not conducting, no path exists, so charge stays → $V_{out}$ remains $V_{DD}$ (logic 1) — held only by trapped charge.

Worked Examples

Worked example Example 3 — Charge sharing failure (why fragile)

Dynamic gate PDN = $A$ (top) in series with $B$ (bottom), output cap $C_L$ , internal node between them has cap $C_X$ . Precharge to $V_{DD}$ ; internal node was left at 0.

Evaluate with $A=1, B=0$ : path to ground is still open (B off), so logically $Y$ should stay HIGH.
BUT turning $A$ on connects $C_L$ to the discharged $C_X$ . Charge redistributes: $V_{final}=V_{DD}\cdot\frac{C_L}{C_L+C_X}.$ Why this step? Total charge $Q=C_L V_{DD}$ spreads over $C_L+C_X$ . If $C_X$ is comparable to $C_L$ , $V_{out}$ droops → possible false 0. Fix: precharge internal nodes too, or add a keeper.

Common Mistakes (Steel-manned)

Imagine a water tank on the roof (that's the output). Every night you fill it up (precharge). During the day, there's a chain of doors (the input switches) leading to a drain. If all the right doors open, the water empties out (output = 0). If the doors stay shut, the water stays full (output = 1). The clever trick: you don't need a pump running all day — you just fill once and let the tank remember by holding water. The downside: water slowly leaks, and if you connect the tank to an empty pipe, the level drops (charge sharing). So you must refill every cycle.

Flashcards

What are the two phases of a dynamic CMOS gate?

Precharge (

\phi=0

, output charged to

V_{DD}

by PMOS) and Evaluate (

\phi=1

, conditional discharge through NMOS PDN).

How many transistors does an N-input dynamic gate need vs static CMOS?

About

N+2

(PDN + precharge PMOS + foot NMOS) vs

2N

for static.

What logic function does a dynamic gate realize given its PDN?

f=\overline{\text{PDN conducts}}

; series NMOS → NAND-type, parallel NMOS → NOR-type.

Why is the foot (evaluation) NMOS needed?

To break the ground path during precharge so the output can charge fully and avoid a static short-circuit path.

Why can't dynamic logic hold its output indefinitely?

A logic 1 is only trapped charge on

C_L

; leakage bleeds it away, so it must be refreshed each cycle (or use a keeper).

What is charge sharing and its effect?

When the output cap

C_L

connects to a discharged internal node

C_X

; charge redistributes to

V_{DD}\,C_L/(C_L+C_X)

, drooping the output → possible false 0.

Why can't dynamic gates be directly cascaded?

Outputs are HIGH during precharge; feeding that into another dynamic PDN can wrongly discharge it. Inputs must be monotonic

0\to1

during evaluate.

What is Domino logic and what does it fix?

A static inverter added after each dynamic gate so its output is LOW during precharge and rises only

0\to1

, allowing safe cascading.

In dynamic logic, why is only an NMOS PDN used (no PUN)?

The pull-up job is done by the clocked precharge PMOS; eliminating the PUN is the whole source of transistor savings.

What is a keeper transistor?

A weak PMOS feeding output back to hold the HIGH level against leakage and charge sharing.

Connections

Static CMOS logic — the $2N$ -transistor baseline dynamic logic optimizes.
Domino logic — fixes the cascading/monotonicity problem.
Charge sharing and keepers — reliability countermeasures.
MOS capacitance and $C_L$ — why charge storage and leakage matter.
Clocking and precharge timing — the $\phi$ that separates the two phases.
Pull-down networks (series = AND, parallel = OR) — how to synthesize the PDN.

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, static CMOS mein har gate ke liye do networks lagte hain — ek pull-up (PMOS) aur ek pull-down (NMOS). Yeh safe hai par transistor bahut lagte hain ( $2N$ ). Dynamic CMOS ka jugaad simple hai: output ko ek capacitor ki tarah socho. Pehle clock LOW hone par ek PMOS output ko $V_{DD}$ tak charge kar deta hai (precharge). Phir clock HIGH hone par woh PMOS band, aur ek foot NMOS on hota hai — ab sirf NMOS pull-down network (PDN) decide karta hai ki charge nikalega ya nahi (evaluate). Agar PDN conduct karta hai to output 0, warna charge trapped rehta hai aur output 1 rehta hai.

Fayda kya hai? Poora PUN hata diya — bas ek precharge PMOS aur ek foot NMOS, matlab $N+2$ transistors. Chota, tez, kam power (koi bhi phase mein VDD-to-GND direct short nahi). Function bhi simple: series NMOS lagao to NAND, parallel NMOS lagao to NOR — bas output pe "NOT" laga do ( $f=\overline{PDN}$ ).

Lekin muft mein kuch nahi milta. Yeh logic fragile hai. Ek — logic 1 sirf charge hai, leakage se dheere-dheere gir jaata hai, isliye har cycle refresh karna padta hai (ya ek weak keeper PMOS lagao). Do — charge sharing: agar output cap ka charge kisi discharged internal node ke saath share ho jaye to voltage $V_{DD}\,C_L/(C_L+C_X)$ tak gir sakta hai, galat 0 ban sakta hai. Teen — dynamic gates ko seedha cascade nahi kar sakte, kyunki precharge ke time sab outputs HIGH hote hain, jo agle gate ko galat discharge kar dete hain. Iska fix hai Domino logic — har dynamic gate ke baad ek static inverter laga do. Exam mein yeh teen weaknesses aur " $f=\overline{PDN}$ , $N+2$ transistors" — yahi 80/20 hai.

WHAT it is

WHY it works — derive the two phases from first principles

Worked Examples

Common Mistakes (Steel-manned)

The 80/20 core

Feynman

Flashcards

Connections

Concept Map

Hinglish (regional understanding)

Go deeper — visual, from zero

Test yourself — CMOS Circuit Design

Connections