Dynamic CMOS logic: Foundations — Hardware deep dive

Before you can read the parent note Dynamic CMOS logic, you must own every symbol it throws at you. This page builds them one at a time — plain words, then a picture, then why the topic needs it. Nothing is used before it is defined.

1. Voltage, and the two magic levels $0$ and $V_{D D}$

The picture: think of a water tower. Height above the ground = voltage. A full tower is $V_{D D}$ ; an empty one is $0$ .

Why the topic needs it. The whole trick of dynamic logic is watching a voltage rise to $V_{D D}$ and then possibly fall to $0$ . If you don't picture voltage as a height, the words "precharge HIGH" and "discharge to 0" are meaningless.

2. The output node and its voltage $V_{o u t}$

Why the topic needs it. Everything in dynamic logic — precharge, discharge, leakage, charge sharing — is a statement about how $V_{o u t}$ moves over time. We define it now, before any equation uses the symbol.

3. Charge $Q$ , load capacitance $C_{L}$ , and the equation $Q = C_{L} V_{o u t}$

The picture: a bucket of water. Width of the bucket = $C_{L}$ . Water height = $V_{o u t}$ . Volume of water = $Q$ . A wide bucket ( $C_{L}$ big) holds lots of charge even at a modest height.

Why the topic needs it. The parent note's central formula $Q = C_{L} V_{o u t}$ and the charge-sharing formula both come straight from this bucket. $C_{L}$ is specifically the total load capacitance at the output node; see MOS capacitance and $C_L$ for where it physically comes from (gate caps of the next stage + wire + drain caps).

4. Current $I$ and the rate equation $I = C_{L} \frac{d V _{o u t}}{d t}$

Now we need a tool: how fast does the bucket's height change when water flows? Start from $Q = C_{L} V_{o u t}$ and ask "how does $Q$ change over time?"

The picture: a wider bucket ( $C_{L}$ large) fills or drains slower for the same pipe flow — that is why big load caps make gates slow.

Why the topic needs it. During evaluate, current $I$ drains through the pull-down transistors; this equation tells you the output falls at a definite speed, not instantly. It is the reason "faster" and "slower" gates even exist.

5. The transistor as a switch: NMOS and PMOS

The threshold symbols $V_{t n}$ , $V_{tp}$ and $V_{GS}$ . The gate-to-source voltage is written $V_{GS} = V_{g a t e} - V_{so u r ce}$ . A transistor only turns on once $V_{GS}$ crosses its threshold voltage:

An NMOS turns on when $V_{GS}$ rises above a small positive number $V_{t n}$ (its threshold, e.g. $+ 0.4 V$ ).
A PMOS turns on when $V_{GS}$ falls below a small negative number $V_{tp}$ (e.g. $- 0.4 V$ ).

That is why the parent note writes $V_{GS} = 0 - V_{D D} = - V_{D D} < V_{tp}$ → ON: the PMOS gate is at $0$ , the source at $V_{D D}$ , so $V_{GS}$ is very negative — well past its (negative) turn-on point. By the same rule, the foot NMOS with gate at $V_{D D}$ and source at ground has $V_{GS} = + V_{D D} > V_{t n}$ → ON.

Why the topic needs it. The precharge device is a PMOS; the pull-down network and the foot are NMOS. You cannot follow "which device is on in which phase" without this rule.

6. The precharge PMOS and the foot NMOS

The picture: $M_{p}$ is the tap at the top of the bucket; $M_{e}$ is a master valve at the very bottom drain. If the master valve $M_{e}$ is shut, no water can leave no matter which doors above are open.

Why the topic needs it. These are the two devices the clock $ϕ$ (next section) toggles. Naming and picturing them now means the phase story reads cleanly. The foot NMOS is also what stops a short-circuit during precharge — see the note in §5 on why $M_{p}$ and $M_{e}$ are never both draining at once.

7. The clock $ϕ$ , its two phases, and the non-overlap gap

The picture: a metronome. Down-beat = fill the bucket. Up-beat = decide whether to empty it. See Clocking and precharge timing for how long each phase must last.

Why the topic needs it. Dynamic logic is timed logic. The same physical wire ( $ϕ$ ) drives $M_{p}$ 's gate and $M_{e}$ 's gate — so one signal flips the whole gate between "fill" and "compute". Because PMOS and NMOS are mirror-image switches (§5), when $ϕ = 0$ the PMOS is on and the foot NMOS is off; when $ϕ = 1$ they swap. The dead-time keeps that swap clean.

8. Pull-Down Network (PDN): series vs parallel

The picture: series = a single hallway with several doors; you get through only if ALL doors are open. Parallel = several separate hallways; you get through if ANY one is open.

Why the topic needs it. The realized function is $f = \overline{PDN conducts}$ . Series → NAND, parallel → NOR. This is the bridge from "wires and switches" to "Boolean algebra". Deep-dive: Pull-down networks (series = AND, parallel = OR).

Why the topic needs it. Leakage and charge sharing are why a bare dynamic gate is fragile; the keeper is the standard fix that makes a stored 1 survive. Full treatment: Charge sharing and keepers.

10. Cascading, the static inverter, and Domino

Why the topic needs it. It explains the mysterious rule "you cannot chain dynamic gates directly." It builds directly on §5 (NMOS on with HIGH) and §7 (all outputs HIGH during precharge).

Prerequisite map

Equipment checklist

Test yourself — cover the right side and answer out loud.

What is the output node, and what does

V_{o u t}

mean?

The single wire carrying the gate's answer;

V_{o u t}

is its voltage vs ground — near

V_{D D}

= logic 1, near

0

= logic 0.

Logic 1 and logic 0 are physically what?

A node sitting near

V_{D D}

volts, or near

0

volts.

What does

C_{L}

stand for and where does it live?

The total load capacitance at the output node (next-stage gate caps + wire + drain caps).

What does

Q = C_{L} V_{o u t}

say in bucket words?

Stored charge = bucket width

C_{L}

times water height

V_{o u t}

Why does

\frac{d V _{o u t}}{d t}

appear, and what does it measure?

Because current is a rate of charge flow; it measures how fast the output voltage is changing right now.

When does an NMOS conduct? A PMOS?

NMOS conducts when

V_{GS} > V_{t n}

(gate HIGH); PMOS conducts when

V_{GS} < V_{tp}

(gate LOW).

What are the signs of

V_{t n}

and

V_{tp}

V_{t n}

is positive (NMOS threshold);

V_{tp}

is negative (PMOS threshold).

What are the precharge PMOS and foot NMOS for?

M_{p}

fills the output to

V_{D D}

;

M_{e}

opens/blocks the drain path to ground.

Why is

V_{GS} = - V_{D D} < V_{tp}

during precharge?

The PMOS gate is at

0

and source at

V_{D D}

, so

V_{GS}

is strongly negative — past its negative threshold, so it's ON.

What are

ϕ = 0

and

ϕ = 1

, and why the dead-time?

Precharge (

ϕ = 0

) and Evaluate (

ϕ = 1

); a non-overlap gap prevents shoot-through current when the two clocked devices swap.

Series NMOS realizes which Boolean op? Parallel?

Series = AND (all must conduct); parallel = OR (any conducts).

What is the charge-sharing final voltage formula?

V_{f ina l} = V_{D D} C_{L} / (C_{L} + C_{X})

What is a keeper and what does it fix?

A weak feedback PMOS that tops up the output bucket to cancel leakage, keeping a stored 1 valid.

What is a static inverter and why add it after a dynamic gate?

A one-PMOS-one-NMOS gate that flips its input and always drives firmly; added to make Domino cascades default LOW and rise only

0 \to 1

Why can't dynamic gates be cascaded directly?

All outputs are HIGH during precharge, which can wrongly discharge the next stage — fixed by Domino logic.