Dynamic CMOS logic: Worked examples — Hardware deep dive

This deep dive takes the parent gate and drives it through every case that a real chip (or exam) can throw at it. We start with the small circuit facts every example uses, then build a matrix of scenarios, then solve one example per cell.

Intuition The one picture that runs the whole page

The output node is a bucket of charge sitting on a capacitor $C_{L}$ . "Capacitance" just means how much charge you must pour in to raise the voltage by one volt — a fatter bucket needs more charge for the same level. See MOS capacitance and $C_L$. Two clock phases act on that bucket: precharge fills it to $V_{D D}$ ; evaluate either drains it (through the NMOS pull-down network) or leaves it full. The figure below is the picture every example returns to.

Figure s01 — The master circuit: a white $V_{D D}$ rail at top feeds a blue precharge PMOS ( $M_{p}$ , gated by clock $ϕ$ ) into the yellow output node $V_{o u t}$ ; a green $C_{L}$ "bucket" hangs off $V_{o u t}$ to ground; below the node sits the green PDN switch block, then the yellow foot NMOS $M_{e}$ (labelled "off in precharge, on in evaluate"), then the white ground symbol.

Read it left-to-right: the blue precharge PMOS fills the bucket $C_{L}$ ; the yellow foot NMOS $M_{e}$ (defined next) gates the drain; the green PDN switches decide whether the water runs out.

The scenario matrix

Every case a dynamic gate can hand you falls into one of these cells. The examples below are each tagged with the cell they cover.

Cell	What changes	The question it forces
A. Series PDN, conducting	all inputs 1	Does it discharge to a clean 0?
B. Parallel PDN, one input 1	exactly one branch on	Does one branch drain the whole node?
C. Non-conducting (hold)	PDN path broken	Does the trapped charge stay HIGH?
D. Degenerate: no foot NMOS	inputs high during precharge	What breaks without $M_{e}$ ?
E. Charge sharing (real, $V_{t n}$ -clamped)	internal node $C_{X}$ discharged	How far does $V_{o u t}$ droop, valve limited?
F. Limiting values of $C_{X}$	$C_{X} \to 0$ and $C_{X} \to \infty$	Best case vs worst case droop
G. Leakage over time	hold phase, current leaks	How long until the 1 rots?
H. Coupling / charge injection	neighbour swings down or up, clock kick	Does the extra charge push a false level?
I. Cascading (monotonicity)	dynamic output → dynamic input	Why does it glitch, and the fix
J. Word problem	real timing budget	Pick a clock period that works
K. Exam twist	keeper sizing	Does the keeper win the fight?

Worked examples

Cell A — series PDN, full conduction

Worked example Example 1 — Dynamic 2-input NAND, both inputs high

Setup: $A$ and $B$ NMOS in series, $V_{D D} = 1.0$ V, $C_{L}$ precharged to $V_{D D}$ . Evaluate with $A = B = 1$ .

Forecast: guess the final $V_{o u t}$ and the logic value before reading on.

Precharge phase. $ϕ = 0$ : PMOS on, foot $M_{e}$ off, $V_{o u t} \to 1.0$ V. Why this step? The default (non-discharged) value of a NAND is 1, so we must start at 1.
Enter evaluate. $ϕ = 1$ : PMOS off, foot NMOS $M_{e}$ on. Why this step? We hand control of the bucket to the pull-down network.
Both series NMOS conduct (both gates at 1). A continuous wire now links $C_{L}$ to ground. Why this step? Series means AND: the path exists only when every switch is closed. See Pull-down networks (series = AND, parallel = OR).
Charge drains fully: $V_{o u t} \to 0$ V. Logic value $= \overline{A \cdot B} = \overline{1 \cdot 1} = 0$ . Why this step? Ground is a bottomless sink; with a path open, $Q \to 0$ , so $V = Q / C_{L} \to 0$ .

Verify: $\overline{1 \cdot 1} = 0$ ✓. Final voltage $0$ V is a clean logic 0 (well below the danger zone). ✓

Cell B — parallel PDN, exactly one branch on

Cell C — non-conducting, the HOLD case

Cell D — degenerate: the foot NMOS removed

Worked example Example 4 — What breaks with no

$M_{e}$ Setup: dynamic NAND without the foot transistor $M_{e}$ (defined in the intro). During precharge ( $ϕ = 0$ ) the inputs happen to be $A = B = 1$ .

Forecast: can the node reach $1.0$ V?

Precharge PMOS on, trying to pull $V_{o u t} \to V_{D D}$ .
But with no foot $M_{e}$ , the series $A$ – $B$ NMOS (both on) also connect $V_{o u t}$ to ground. Why this step? $M_{e}$ was the only switch that broke the ground path during precharge; remove it and nothing blocks the pull-down.
A direct $V_{D D} \to$ ground path exists → static short-circuit current flows; $V_{o u t}$ settles at a resistive divider value, not a clean 1. Why this step? Two "on" resistors fighting between rails set a mid voltage — the danger zone.

Verify: the failure is qualitative — the node cannot precharge cleanly and burns static power. Adding $M_{e}$ (off during precharge) breaks the ground path. See the foot-NMOS mistake in the parent note. ✓

Worked example Example 5 — Droop from a discharged internal node

Setup: series NAND, $A$ on top, $B$ below, internal node between them has $C_{X} = 20$ fF and was left at $0$ V. Output $C_{L} = 50$ fF, precharged to $V_{D D} = 1.0$ V. Evaluate with $A = 1$ , $B = 0$ (logically a HOLD → should stay 1). Gate $A$ is driven to $V_{D D} = 1.0$ V; NMOS threshold $V_{t n} = 0.4$ V.

Forecast: should be 1, but guess the actual voltage after $A$ turns on. Will the internal node fully charge up?

Before: $Q_{L} = C_{L} V_{D D} = 50 fF \times 1.0 = 50$ fC on the output; $Q_{X} = 0$ on the internal node. Why this step? $Q = C V$ gives the starting charge in each bucket.
Check the valve first. The NMOS $A$ is a source follower: it can only raise the internal node up to $V_{g a t e} - V_{t n} = 1.0 - 0.4 = 0.6$ V. Above that, $A$ shuts off on its own. Why this step? An NMOS pass transistor is a one-way valve, not an ideal wire (see the $V_{t n}$ definition). We must test whether pure capacitive sharing would exceed this clamp.
Pure capacitive-division guess (upper bound): if $A$ were an ideal wire, both buckets equalise: $V_{i d e a l} = V_{D D} \frac{C _{L}}{C _{L} + C _{X}} = 1.0 \times \frac{50}{70} = 0.714 V .$ The internal node would want to rise to $0.714$ V — but the valve clamps it at $0.6$ V. So the transistor stops passing charge early. Why this step? We compare the ideal shared voltage against the $V_{t n}$ clamp to see which limits us.
Real settling. The internal node stops at $V_{X} = 0.6$ V (valve-limited), so it absorbed only $Q_{X}^{'} = C_{X} \times 0.6 = 20 \times 0.6 = 12$ fC. That charge left the output: $Q_{L}^{'} = 50 - 12 = 38$ fC, giving $V_{o u t} = \frac{Q _{L}^{'}}{C _{L}} = \frac{38}{50} = 0.76 V .$ Why this step? Charge conservation, but only the charge that actually crossed the valve (12 fC) is removed from $C_{L}$ . The valve leaves the output higher than the ideal-wire estimate.

The plot below traces both curves — the naive capacitive division (over-pessimistic) and the real $V_{t n}$ -clamped droop; the yellow dot is this example.

Figure s02 — Charge-sharing droop vs internal capacitance $C_{X}$ (fF) on the x-axis, shared output voltage $V_{o u t}$ (V) on the y-axis. A blue curve shows the naive ideal-wire division $V_{D D} C_{L} / (C_{L} + C_{X})$ falling from 1 V toward 0; a green curve shows the real $V_{t n}$ -clamped result, which stays higher because the NMOS valve stops passing charge at 0.6 V. A yellow dot marks Example 5 (real 0.76 V), a red dot marks the $C_{X} = C_{L}$ ideal 0.5 V case, and a dashed green line marks the input threshold $V_{t h} = 0.6$ V.

Verify: ideal $50/70 = 0.714$ ; valve-clamped real answer $0.76 > 0.714$ (the valve helps). Since $0.76 > V_{t h} = 0.6$ V, this survives comfortably. Ignoring $V_{t n}$ would have underestimated $V_{o u t}$ . Fix for worse cases: precharge $C_{X}$ too, or add a keeper. See Charge sharing and keepers. ✓

Cell F — limiting values of $C_{X}$

Worked example Example 6 — Best case and worst case droop (with the valve)

Setup: same gate, $V_{D D} = 1.0$ V, $C_{L} = 50$ fF, $V_{t n} = 0.4$ V so the valve clamp is $V_{c l am p} = V_{D D} - V_{t n} = 0.6$ V. Push $C_{X}$ to both extremes. The internal node absorbs at most $C_{X} \times V_{c l am p}$ of charge, so the real worst-case output is $V_{o u t} = \frac{C _{L} V _{D D} - m i n ( C _{X} V _{c l am p} , ideal share )}{C _{L}} .$

Forecast: what happens as the internal cap vanishes vs blows up?

$C_{X} \to 0$ : no bucket to share with. $V_{o u t} = 1.0$ V. Why this step? Zero internal cap absorbs zero charge — no droop either way.
$C_{X} = C_{L} = 50$ fF: ideal division would give $0.5$ V, but the valve clamps the internal node at $0.6$ V, so it absorbs only $C_{X} \times 0.6 = 30$ fC. Output $= (50 - 30) /50 = 0.4$ V. Why this step? Even valve-limited, a big $C_{X}$ drops us to $0.4$ V — below $V_{t h} = 0.6$ V, a false 0. (The naive answer $0.5$ V was actually optimistic here because $30 > 25$ fC crosses.)
$C_{X} \to \infty$ : the internal node stays near $0$ V no matter how much charge arrives, and the valve keeps passing charge until $C_{L}$ falls to the clamp region. In the limit $V_{o u t} \to V_{c l am p} = 0.6$ V (the valve shuts off once the output side can no longer push above the clamp) — not all the way to 0 as the naive model claimed. Why this step? The one-way valve floors the collapse: it stops conducting once the drop across it falls below $V_{t n}$ . This is the key correction to the ideal-wire picture.

Verify: $C_{X} \to 0$ : $1.0$ V ✓. $C_{X} = C_{L}$ : $(50 - 30) /50 = 0.4$ V, and $0.4 < 0.6$ → false 0 ✓. $C_{X} \to \infty$ : floored at $V_{c l am p} = 0.6$ V, strictly above the naive limit of $0$ ✓. The valve makes charge sharing less catastrophic than pure capacitive division predicts. ✓

Cell G — leakage over time

Worked example Example 7 — How long does the 1 survive?

Setup: node holds logic 1 at $V_{D D} = 1.0$ V on $C_{L} = 50$ fF. A constant leakage current $I_{l e ak} = 1$ nA bleeds it. The next gate misreads once $V_{o u t}$ falls below the threshold $V_{t h} = 0.6$ V (defined in the intro).

Forecast: microseconds? nanoseconds? guess the hold time.

Constant current draining a capacitor: from $I = C_{L} d V / d t$ , a fixed $I$ gives a straight-line voltage ramp down. Why this tool? $I = C d V / d t$ is the defining law of a capacitor; with $I$ constant it integrates to $Δ V = I t / C_{L}$ . No exponential is needed because the current here is modeled constant.
Allowed drop $Δ V = 1.0 - 0.6 = 0.4$ V. Why this step? That's the margin before $V_{o u t}$ crosses $V_{t h}$ and gets misread.
Hold time $t = \frac{C _{L} Δ V}{I _{l e ak}} = \frac{50 \times 1 0 ^{- 15} \times 0.4}{1 \times 1 0 ^{- 9}}$ s. Why this step? Rearranged from $Δ V = I t / C_{L}$ .
$t = 20 \times 1 0^{- 6}$ s $= 20 μ$ s. Why this step? Plug numbers; units: $F \cdot V / A = C / A = s$ ✓.

Verify: $50 \times 1 0^{- 15} \times 0.4 = 2 \times 1 0^{- 14}$ C; divided by $1 0^{- 9}$ A gives $2 \times 1 0^{- 5}$ s $= 20 μ$ s ✓. So the clock must re-precharge faster than 20 µs — trivially true at MHz+ speeds, but a keeper removes the constraint entirely.

Cell H — coupling / charge injection, both directions

Worked example Example 8 — Aggressor swings down, then up, plus a clock kick

Setup: the held-1 node ( $C_{L} = 50$ fF at $1.0$ V) sits next to a switching wire sharing a coupling capacitance $C_{c} = 5$ fF. We test three sub-cases. (This is the third charge phenomenon promised in the intro — coupling, alongside charge sharing and leakage.)

Forecast: a tiny 5 fF coupling versus a 50 fF bucket — negligible each way, or enough to matter?

A voltage step $Δ V_{a g g}$ on one plate of a coupling cap injects charge onto our node through a capacitive divider: $Δ V_{o u t} = Δ V_{a g g} \cdot \frac{C _{c}}{C _{c} + C _{L}} .$ Why this tool and not charge sharing? Nothing is being discharged to share; instead a moving plate pushes charge across $C_{c}$ . The kick fraction is $C_{c} / (C_{c} + C_{L}) = 5/55 = 0.0909$ — the same magnitude in either direction.
Sub-case H1 — aggressor swings DOWN by 1.0 V (held-1 victim). $Δ V_{o u t} = - 1.0 \times 0.0909 = - 0.0909$ V → node falls to $1.0 - 0.0909 = 0.909$ V. Why this step? A downward neighbour drags a held 1 toward the danger zone — the worst direction for a stored 1.
Sub-case H2 — aggressor swings UP by 1.0 V (held-0 victim, e.g. a node already discharged during evaluate). $Δ V_{o u t} = + 1.0 \times 0.0909 = + 0.0909$ V → a node meant to be $0$ V gets kicked up to $0.0909$ V. Why this step? An upward neighbour lifts a logic 0. Here $0.0909 < V_{t h} = 0.6$ V so it is still read as 0 — safe — but a stronger coupling or a smaller noise margin could push it over into a false 1. Both polarities matter.
Sub-case H3 — clock-feedthrough kick. When the precharge PMOS or foot NMOS switches, its gate-to-drain overlap capacitance $C_{g d}$ (see MOS capacitance and $C_L$) injects charge the same way. Model it as $C_{c}^{'} = 2$ fF driven by the clock edge $Δ V = 1.0$ V: $Δ V_{o u t} = 1.0 \times 2/ (2 + 50) = + 0.0385$ V. Why this step? Clock feedthrough is just coupling where the "aggressor" is the clock itself — it always fires, every cycle, so it adds a fixed offset to every held node.

Verify: H1: $5/55 = 0.0909$ , node $0.909$ V $> V_{t h}$ , survives ✓. H2: $+ 0.0909$ V, still $< 0.6$ V, reads 0 ✓. H3: $2/52 = 0.0385$ V ✓. Downward kicks threaten held 1s, upward kicks threaten held 0s — you must budget noise margin for both. A keeper fights the downward case; keeping aggressors quiet during evaluate fights the upward case. ✓

Cell I — cascading and monotonicity

Worked example Example 9 — Why two dynamic gates in a row glitch

Setup: dynamic gate 1's output feeds an NMOS input of dynamic gate 2. Both share clock $ϕ$ .

Forecast: both go HIGH during precharge — is that a problem for gate 2?

During precharge, every dynamic output is HIGH ( $= 1$ ). Why this step? Precharge blindly charges all output nodes to $V_{D D}$ .
At the start of evaluate, gate 2 sees its input already at 1 — its PDN branch may discharge gate 2 before gate 1's real value (which might be $0$ ) arrives. Why this step? A dynamic PDN can only tolerate an input that transitions $0 \to 1$ during evaluate; a $1 \to 0$ glitch has already stolen the charge before the correct value settles.
This is a monotonicity violation — the false early 1 causes an irreversible wrong discharge of gate 2. Why this step? Once the bucket empties there is no way to re-fill it until the next precharge; the wrong answer is latched for the rest of the cycle.

The timing trace below shows gate 1 still HIGH at the evaluate edge, wrongly draining gate 2.

Figure s03 — Stacked timing waveforms over one clock cycle (x-axis time, split into a "precharge" then "evaluate" region by a dashed yellow line). Top white trace is the clock $ϕ$ ; middle blue trace is gate 1's output, still HIGH at the evaluate edge (annotated in red "still HIGH at eval start, false early 1"); bottom red trace is gate 2's output collapsing to 0 (annotated "wrong discharge, monotonicity violation").

Verify: the failure is logical, not numeric: any input still HIGH at the evaluate edge can wrongly discharge the next stage. The fix is Domino logic — put a static inverter after each dynamic gate so its output is LOW during precharge and can only rise $0 \to 1$ during evaluate, guaranteeing every downstream input is monotone. ✓

Cell J — word problem, timing budget

Worked example Example 10 — Pick a clock period

Setup: A dynamic block needs $t_{p r e} = 200$ ps to precharge and $t_{e v a l} = 350$ ps to evaluate (worst-case discharge). Precharge and evaluate happen in separate clock half-phases of equal length. What is the minimum clock period $T$ , and the max frequency?

Forecast: just add them? or double the bigger one?

General rule first. Each half-phase lasts $T /2$ and must contain its own operation, so both must fit: $\frac{T}{2} \geq t_{p r e} and \frac{T}{2} \geq t_{e v a l} ⟹ \frac{T}{2} \geq max (t_{p r e}, t_{e v a l}) .$ Why this step? A 50% duty clock spends $T /2$ in $ϕ = 0$ and $T /2$ in $ϕ = 1$ ; the binding constraint is whichever operation is longer. See Clocking and precharge timing.
Here $max (200, 350) = 350$ ps, so $T /2 \geq 350$ ps. Why this step? Evaluate is the longer operation for these numbers; if precharge were longer, it would set the bound instead.
$T \geq 2 \times 350 = 700$ ps. Max frequency $f = 1/ T = 1/ (700 \times 1 0^{- 12})$ Hz. Why this step? Frequency is the reciprocal of period.
$f \approx 1.43 \times 1 0^{9}$ Hz $\approx 1.43$ GHz.

Verify: $2 \times 350 = 700$ ps ✓; $1/700 ps = 1.4286 \times 1 0^{9}$ Hz $\approx 1.43$ GHz ✓. (The 200 ps precharge easily fits in the 350 ps half — as the general rule predicts, only the larger operation binds.)

Cell K — exam twist, keeper sizing

Worked example Example 11 — Does the keeper hold the node?

Setup: A weak feedback keeper PMOS can source $I_{k ee p} = 0.5$ nA into the held node. Leakage tries to drain $I_{l e ak} = 0.3$ nA. Does the logic-1 survive indefinitely? Then re-check with an undersized keeper of $I_{k ee p} = 0.2$ nA.

Forecast: keeper current vs leakage current — who wins?

Net current onto the node $= I_{k ee p} - I_{l e ak}$ . Why this step? Currents into a node add (Kirchhoff's current law); a positive net keeps the bucket topped up.
Sized keeper: $I_{n e t} = 0.5 - 0.3 = + 0.2$ nA (into the node). Why this step? Keeper supplies more than leakage removes.
Since $I_{n e t} > 0$ , the node cannot droop — the 1 is held forever ( $d V / d t = I_{n e t} / C_{L} > 0$ , clamped at $V_{D D}$ ). Why this step? A positive current pushes $V$ up, so the held 1 never crosses $V_{t h}$ .
Undersized keeper: $I_{n e t} = 0.2 - 0.3 = - 0.1$ nA (out of the node). Now $d V / d t < 0$ : the node slowly rots exactly like Cell G, just at the reduced net leakage rate. Why this step? A keeper weaker than leakage only slows the droop; it does not stop it — sizing must satisfy $I_{k ee p} > I_{l e ak}$ .

Verify: sized: $0.5 - 0.3 = 0.2 > 0$ → held ✓. Undersized: $0.2 - 0.3 = - 0.1 < 0$ → rots ✓. The design rule is $I_{k ee p} > I_{l e ak}$ , but not so strong it can't be overpowered by the PDN during a legitimate discharge (that would slow evaluate). See Charge sharing and keepers. ✓

Recall Self-test: which cell is each?

A node holds logic 1 only by trapped charge for a finite time — which cell? ::: Cell G (leakage). $V_{o u t}$ droops when $C_{L}$ shares charge with $C_{X}$ , but the NMOS valve floors the drop at $V_{D D} - V_{t n}$ — which cell? ::: Cells E and F (charge sharing, $V_{t n}$ -clamped). A neighbour wire swinging up lifts a held 0; swinging down drags a held 1 — which cell? ::: Cell H (coupling / charge injection, both directions). Two dynamic gates back-to-back cause a monotonicity violation — which cell? ::: Cell I (cascading). Removing the foot NMOS $M_{e}$ gives a precharge short-circuit — which cell? ::: Cell D (degenerate). A weak PMOS refreshes the held node against leakage — which cell? ::: Cell K (keeper sizing). Minimum clock period from precharge/evaluate times — which cell? ::: Cell J (timing budget).

Compare every case against a full-strength Static CMOS logic gate: static never droops, never leaks, never needs a keeper — but pays $2 N$ transistors for that safety. Dynamic trades robustness for speed and area, and this matrix is the price list.