Exercises — Dynamic CMOS logic

• Precharge: $\varphi =0$. Recall what "ON" means for a PMOS: it conducts only when its gate is more than a threshold magnitude $|V_{TH}|$ below its source. Here the source is $V_{DD}$ and the gate is $0$, so $V_{GS}=0-V_{DD}=-V_{DD}$. The precise ON-condition is $V_{GS}<-|V_{TH}|$, i.e. $-V_{DD}<-|V_{TH}|$, which is true as long as $V_{DD}>|V_{TH}|$ (always the case in a working chip). So $Mp$ is comfortably ON, pulling the output to $V_{DD}$. The foot NMOS $Me$ has gate $=0$, so its $V_{GS}=0<V_{TH}$ (NMOS needs $V_{GS}>V_{TH}$ to turn on) → OFF.
• Evaluate: $\varphi =1$. Now $Mp$'s gate is $V_{DD}$, so $V_{GS}=V_{DD}-V_{DD}=0>-|V_{TH}|$ → OFF; $Me$'s gate is $V_{DD}>V_{TH}$ → ON, and the pull-down network decides. WHAT it looks like: picture the output node as a bucket. At $\varphi =0$ you fill it ($Mp$ open, drain valve $Me$ shut). At $\varphi =1$ the fill valve closes and the drain valve opens.

Let $N$ = the number of inputs to the gate; here $N=3$. Dynamic $=\underset{\text{PDN, one NMOS per input}}{\underbrace{N}}+\underset{Mp}{\underbrace{1}}+\underset{Me}{\underbrace{1}}=N+2=3+2=5$. Static CMOS needs one PMOS and one NMOS per input (a full PUN plus a full PDN), so Static $=2N=2\times 3=6$. So dynamic saves 1 transistor here; because dynamic grows as $N+2$ while static grows as $2N$, the gap grows for wider gates.

Parallel NMOS conducts if any input is 1 → discharge condition is $A+B+C+D$. The output is $Y=\overline{A+B+C+D}$ — a 4-input NOR. (See Pull-down networks (series = AND, parallel = OR): parallel = OR inside the bar.)

PDN: three NMOS in series (series = AND). Why series? A series chain conducts only when all gates are 1, matching the discharge condition $A\cdot B\cdot C$.

• $(1,1,1)$: whole chain conducts → output discharges → $Y=0=\overline{1\cdot 1\cdot 1}$. ✓
• $(1,0,1)$: middle transistor off → chain broken → node stays precharged → $Y=1=\overline{1\cdot 0\cdot 1}$. ✓

The discharge expression is $AB+C$.

• $AB$ (an AND) → $A$ and $B$ in series.
• $+C$ (an OR) → put $C$ in parallel with that series pair. So: branch 1 = ($A$ series $B$); branch 2 = ($C$); the two branches in parallel between output node and the foot NMOS $Me$.
• $A=B=1$: branch 1 conducts → $Y=0$.
• $C=1$ alone: branch 2 conducts → $Y=0$.
• $A=1,B=0,C=0$: no branch conducts → $Y=1$. ✓ ($\overline{0+0}=1$.)

During precharge $\varphi =0$ → foot NMOS $Me$ OFF. With all inputs high, the series NMOS chain is fully conducting. If $Me$ were absent (or on), current would flow $V_{DD}\to Mp\to \text{PDN}\to$ ground: a static short-circuit, wasting power and preventing the node reaching $V_{DD}$. $Me$ breaks the ground path, so precharge succeeds no matter what the inputs are.

Read the figure first. On the LEFT (BEFORE), all the charge lives on the big orange $C_L$ at $1.8\text{ V}$, while the small dashed $C_X$ sits empty at $0\text{ V}$ — the top transistor $A$ is still off, so they are isolated. The purple arrow marks the moment $A$ turns on. On the RIGHT (AFTER), $C_L$ and $C_X$ are now connected, so the same charge has spread across both and both boxes sit at the drooped level $1.44\text{ V}$. The figure is the picture behind the formula below. WHY this formula: total charge is conserved. Before sharing, all charge sits on $C_L$: $Q=C_L{V}_{DD}$. After the top transistor connects $C_L$ to the empty $C_X$, that same charge spreads over the combined capacitance $C_L+C_X$: $V_{final}=\frac{Q}{C_L+C_X}=V_{DD}\cdot \frac{C_L}{C_L+C_X}.$ Plug in: $V_{final}=1.8\cdot \frac{20}{20+5}=1.8\cdot \frac{20}{25}=1.8\cdot 0.8=1.44\text{ V}.$ $1.44\text{ V}>0.9\text{ V}$, so it still reads HIGH — no false 0 this time. But the $0.36\text{ V}$ droop (visible as the fading orange in the figure) eats noise margin; larger $C_X$ would flip it. See Charge sharing and keepers.

WHY the numerator is $C_L$ (restated): the charge trapped by the precharge lives on the output cap $C_L$, so the conserved quantity is $Q=C_L{V}_{DD}$ — that is why $C_L$ (not $C_X$) sits on top. When the top transistor connects $C_L$ to the empty $C_X$, this same $Q$ spreads over the combined $C_L+C_X$, giving $V_{final}=Q/(C_L+C_X)=V_{DD}{C}_L/(C_L+C_X)$. Now with $C_X=25\text{ fF}$: $V_{final}=1.8\cdot \frac{20}{20+25}=1.8\cdot \frac{20}{45}=1.8\cdot 0.4444=0.8\text{ V}.$ $0.8\text{ V}<0.9\text{ V}$ → below the next stage's threshold → this is now a false 0. The output should have stayed 1 (path to ground was open) but charge sharing dragged it under threshold. This is exactly the failure the parent note warned about.

WHY $I=CdV/dt$: current is the rate charge leaves the cap, $I=dQ/dt$. On a capacitor $Q=C_{L}V$, so differentiating (with $C_L$ fixed) gives $dQ/dt=C_{L}dV/dt$; hence $I=C_{L}dV/dt$. With constant $I$, $dV/dt$ is constant, so voltage falls linearly and $t=C_L\Delta V/I$. Allowed droop $\Delta V=1.8-0.9=0.9\text{ V}$. $t=\frac{C_L\Delta V}{I_{leak}}=\frac{20\times 10^{-15}\cdot 0.9}{1\times 10^{-12}}\text{ s}.$ Numerator $=1.8\times 10^{-14}$. Divide by $10^{-12}$: $t=1.8\times 10^{-2}\text{ s}=18\text{ ms}$. So the value is safe for ~18 ms — the clock period must be shorter than this (or add a keeper). Compare with Clocking and precharge timing.

Discharge expression $=A(B+C)$.

• $A$ is ANDed with everything → put $A$ in series with the rest (top of the stack).
• $(B+C)$ is an OR → $B$ parallel $C$. So the PDN is: $A$ in series with ($B\parallel C$), all above the foot NMOS $Me$.
• $(A,B,C)=(1,1,0)$: $A$ on, $B$ on → path conducts → $Y=0=\overline{1(1+0)}$. ✓
• $(1,0,0)$: $A$ on but $B\parallel C$ both off → no path → $Y=1=\overline{1\cdot 0}$. ✓
• $(0,1,1)$: $A$ off → chain broken regardless of $B,C$ → $Y=1=\overline{0(\dots )}$. ✓

The failure: at $\varphi =0$ every dynamic output precharges to $1$. So gate 2's input is a spurious HIGH before gate 1 has actually evaluated. When $\varphi \to 1$ (evaluate), gate 2 starts discharging based on that HIGH input. If gate 1's true result is 0, its output later falls $1\to 0$ — but by then gate 2's node may already be wrongly discharged. Charge lost cannot come back (no path pulls it up during evaluate). A dynamic PDN can only safely tolerate inputs that go $0\to 1$ during evaluate, never $1\to 0$. This is a monotonicity violation. The fix: insert a static inverter after each dynamic gate → Domino logic. Now each stage's output is LOW during precharge and can only rise $0\to 1$ in evaluate — exactly the allowed monotonic direction.

Dynamic NOR: $4$ (parallel PDN) $+1$ ($Mp$) $+1$ ($Me$) $=6$. Static NOR: $2\times 4=8$ — an NMOS parallel PDN plus a 4-PMOS series pull-up stack. Dynamic removes the 4-PMOS series stack. That stack is slow for two compounding reasons:

1. Stack sizing / resistance. Series PMOS resistances add, and holes are less mobile than electrons, so each PMOS is already ~2–3× more resistive than an equal-width NMOS. To hit a target rise-time you must widen every PMOS in the stack (upsizing), which balloons area and input capacitance — a vicious circle that gets worse the deeper the stack.
2. Threshold-drop edge case in deep series PMOS. As you stack PMOS in series, the internal source nodes of the upper devices no longer sit at a clean $V_{DD}$; each device's $V_{GS}$ magnitude is eroded, and the body effect raises the effective $|V_{TH}|$ of the transistors farther from the rail. Their overdrive $|V_{GS}|-|V_{TH}|$ shrinks, so they conduct weakly right at the end of the rise — the last stretch toward $V_{DD}$ crawls, stretching rise-time badly for tall stacks. Replacing that whole stack with one clocked precharge PMOS $Mp$ (which sees a full $V_{DD}$ across it and no series partners) sidesteps both problems → the gate is smaller and faster. This is the headline win of dynamic logic. See Static CMOS logic.

WHY $I=CdV/dt$: leakage is a flow of charge off the node, $I=dQ/dt$. The trapped charge lives on the output cap, $Q=C_{L}V$, so with $C_L$ fixed, $dQ/dt=C_{L}dV/dt$ → $I=C_{L}dV/dt$. Modelling the droop as linear over the period $T$ gives $I=C_L\Delta V/T$, so the tolerable leakage is: $I_{leak}\le \frac{C_L\Delta V}{T}=\frac{20\times 10^{-15}\cdot 0.5}{10\times 10^{-9}}\text{ A}.$ Numerator $=1.0\times 10^{-14}$. Divide by $10^{-8}$: $I_{leak}\le 1.0\times 10^{-6}\text{ A}=1\mu \text{A}$. (In real 20 fF nodes leakage is far below this, so a 10 ns period is comfortably safe.) If leakage ever exceeded the budget, you add a keeper: a weak feedback PMOS that trickles charge back onto the node to replace what leaks. See Charge sharing and keepers.

WHY a divider: during a real discharge, keeper (up) and PDN (down) form a series path $V_{DD}\to R_{keep}\to \text{node}\to R_{pdn}\to$ ground; the node sits at the divider point. Require: $V_{DD}\cdot \frac{R_{pdn}}{R_{pdn}+R_{keep}}\le 0.2V_{DD}\Rightarrow \frac{R_{pdn}}{R_{pdn}+R_{keep}}\le \mathrm{0.2.}$ $R_{pdn}\le 0.2(R_{pdn}+R_{keep})\Rightarrow 0.8R_{pdn}\le 0.2R_{keep}\Rightarrow R_{keep}\ge 4R_{pdn}=20\text{ k}\Omega .$ So the keeper must be at least $20\text{ k}\Omega$ — i.e. weak (much more resistive than the PDN). This is exactly why keepers are drawn as tiny minimum-width devices.

Reasoning about "worst case": droop grows as more internal capacitance gets connected to $C_L$ while ground stays isolated. Exposing more internal nodes = larger total $C_X$ = larger droop. So we want to turn on as many top transistors as possible while keeping at least one lower transistor off to block ground.

• Turn on only $A$ ($B,C$ off): exposes just the top node, $C_X=8\text{ fF}$. $V_{final}=1.8\cdot \frac{20}{20+8}=1.8\cdot \frac{20}{28}=1.286\text{ V}.$
• Turn on $A$ and $B$ ($C$ off, still blocks ground): exposes both internal nodes, $C_X=16\text{ fF}$. $V_{final}=1.8\cdot \frac{20}{20+16}=1.8\cdot \frac{20}{36}=1.0\text{ V}.$ The second pattern ($A=B=1,C=0$) is the worst case: it connects the most internal capacitance while $C$ off still blocks ground, giving the largest droop $V_{final}=1.0\text{ V}$. Fix: precharge the internal nodes too (secondary precharge PMOS), or add a keeper.

Did each phase go the right direction? ::: Precharge ($Mp$) pulls UP to $V_{DD}$; evaluate may pull DOWN through NMOS PDN via $Me$. Charge-sharing fraction? ::: $V_{final}=V_{DD}{C}_L/(C_L+C_X)$ — numerator is $C_L$. Why can't you cascade raw dynamic gates? ::: Precharge makes all outputs HIGH → non-monotonic $1\to 0$ inputs → use Domino. Keeper design rule? ::: Weak PMOS, $R_{keep}\gg R_{pdn}$ (about $\ge 4R_{pdn}$), so it beats leakage but loses to the PDN.