Dynamic CMOS logic: Visual walkthrough — Hardware deep dive

Step 1 — The output is just a bucket of charge

WHAT. Forget transistors for a moment. The output wire of any gate is connected to the input gates of the next gates, to the wire's own metal, and to the drains touching it. All of that stored electricity behaves like one capacitor hanging from the output node to ground. We call its size $C_{L}$ (the "load capacitance"). See MOS capacitance and $C_L$.

WHY. A capacitor is the one component that can remember a voltage even with nothing driving it — it holds charge. Dynamic logic's whole trick is to store the answer as that charge, so we must understand the bucket before we understand the trick.

PICTURE. In the figure the output node is a wire; the red capacitor is the bucket. Its water level is the voltage $V_{o u t}$ .

Step 2 — Fill the bucket: the precharge PMOS

WHAT. Add one PMOS transistor ( $M_{p}$ ) between the power rail $V_{D D}$ and the output node. Its gate is driven by the clock signal $ϕ$ (a square wave that is $0$ then $1$ , forever). We hold $ϕ = 0$ for now.

WHY. A PMOS is a switch that turns ON when its gate is LOW. So with $ϕ = 0$ the switch closes and connects the bucket straight to $V_{D D}$ . That is the fill operation — we call this the precharge phase. We pick PMOS (not NMOS) precisely because it fills strongly to a full $V_{D D}$ with no voltage lost; an NMOS would stop one threshold short.

PICTURE. Red switch closed, arrow of charge flowing from $V_{D D}$ down into the bucket, the level rising to the top line.

Step 3 — Add the drain path: the pull-down network

WHAT. Below the output node, add a stack of NMOS transistors whose gates are the logic inputs ( $A$ , $B$ , …). This stack is the pull-down network (PDN). An NMOS turns ON when its gate is HIGH. Arrange them in series for AND, in parallel for OR — see Pull-down networks (series = AND, parallel = OR).

WHY. This is where the logic lives. The PDN is a door to ground: if the inputs open a complete path, the bucket drains; if they don't, it stays full. Notice we have no pull-up network of transistors at all — that whole half of a Static CMOS logic gate is gone, replaced by the single precharge PMOS of Step 2. That deletion is the entire economic point of dynamic logic.

PICTURE. The bucket on top, a red PDN box in the middle with input wires, and ground at the bottom. A dashed line shows the potential drain path.

Step 4 — Guard the drain during fill: the foot NMOS

WHAT. Between the bottom of the PDN and ground, insert one more NMOS ( $M_{e}$ , the foot or evaluate transistor), gated by the same clock $ϕ$ .

WHY. Look at Steps 2 and 3 together. During precharge ( $ϕ = 0$ ) we are filling the bucket. But what if some inputs are already HIGH? Then the PDN door is open — and we would be pouring water in the top ( $M_{p}$ ) while it runs straight out the bottom to ground. That is a wasteful short circuit, and $V_{o u t}$ might never reach the top. The foot NMOS is OFF when $ϕ = 0$ , so it seals the bottom during fill. Only when $ϕ = 1$ does it open. Skipping it is the classic mistake steel-manned in the parent note.

PICTURE. Same stack, now with the red foot transistor at the bottom shown OPEN (blocked) during precharge — the escape route is corked.

Step 5 — Flip the clock: the evaluate phase

WHAT. Now set $ϕ = 1$ . Two things flip at once: $M_{p}$ (gate now HIGH) turns OFF — the fill hose is disconnected; and $M_{e}$ (gate now HIGH) turns ON — the drain's bottom valve opens. See Clocking and precharge timing.

WHY. The bucket is now full and isolated from the rail. Whether it stays full or empties is decided entirely by the PDN doors — i.e. by the inputs. This is the moment the gate computes.

PICTURE. Left half: $M_{p}$ off (red, disconnected). Right/bottom: $M_{e}$ on. The bucket sits full, waiting.

Step 6 — Read the two outcomes

WHAT. With $ϕ = 1$ and the foot open, split into the only two cases the inputs allow:

Case A — PDN conducts (inputs open a full path). Charge $Q$ pours out through $M_{e}$ to ground. By Step 1's formula, as $Q \to 0$ , $V_{o u t} \to 0$ . Output = logic 0.
Case B — PDN blocked (path incomplete). No charge can leave. $Q$ is trapped, so $V_{o u t}$ stays at $V_{D D}$ . Output = logic 1.

WHY. These are the only two possibilities because a switch network is either connected to ground or it isn't. Combine them: the output is $0$ exactly when the PDN conducts, and $1$ otherwise.

PICTURE. Two buckets side by side. Left (red draining, level dropping to 0) = Case A. Right (sealed, level full) = Case B.

Step 7 — The degenerate case: a bucket that leaks and a bucket that shares

WHAT. Two things can spoil Case B (the "stays 1" case), and both are the same fact from Step 1 biting back: $V_{o u t} = Q / C_{L}$ , so if $Q$ falls or $C_{L}$ grows, the level drops.

Leakage. Even with every door shut, tiny currents (subthreshold, junction) trickle $Q$ away. Over a long enough hold time $V_{o u t}$ sags from 1 toward 0 — a false 0. This is why a dynamic 1 is not permanent.
Charge sharing. Suppose the PDN is $A$ (top) in series with $B$ (bottom), with a small hidden capacitor $C_{X}$ at the node between them, sitting empty. Evaluate with $A = 1, B = 0$ : the door to ground stays shut (good), but turning $A$ on suddenly connects the full bucket $C_{L}$ to the empty $C_{X}$ . The charge that was in $C_{L}$ now spreads over both.

WHY. Total charge is conserved: it was $Q = C_{L} V_{D D}$ , now it sits on capacitance $C_{L} + C_{X}$ . Same $Q$ , bigger denominator $\Rightarrow$ smaller level.

PICTURE. A full red bucket $C_{L}$ connected by an opening valve to an empty bucket $C_{X}$ ; the shared level settles partway down — clearly below the top line.

The one-picture summary

Below: the finished gate on the left (precharge PMOS on top, PDN + foot below, bucket $C_{L}$ on the output), and the clock-driven story on the right — level rises during Precharge, then either drains or holds during Evaluate.

Recall Feynman retelling of the whole walkthrough

We started with an empty output wire and noticed it acts like a bucket of charge — the water level is the logic voltage ( $V_{o u t} = Q / C_{L}$ ). Then we bolted on a PMOS filler run by a clock: when the clock is low, it pours the bucket full to the top ( $V_{D D}$ ). Underneath we hung a stack of NMOS doors — the pull-down network — that can drain the bucket to the floor if the inputs open a complete path; series doors need all inputs on (AND/NAND), parallel doors need any (OR/NOR). We added a foot valve at the very bottom, also clock-run, so that while we're filling, the bottom is corked and no water escapes. Then we flip the clock: the filler shuts, the foot valve opens, and now the doors decide — if they open, the bucket empties (output 0); if they stay shut, the bucket stays full (output 1). That gives the one law $f = \overline{PDN conducts}$ . Finally we saw the fragile side: because the answer is just trapped water, it slowly leaks away, and if the doors connect the bucket to a hidden empty bucket, the water shares and the level droops to $V_{D D} C_{L} / (C_{L} + C_{X})$ — either can fake a 0, which is why real chips add keepers and use Domino logic to cascade safely.