3.2.12CMOS Circuit Design

Domino logic

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WHY does domino logic exist?


Background: how a dynamic gate works


The domino fix

WHAT this buys you — monotonicity. Trace the levels:

Phase Dynamic node XX Output Y=XY = \overline{X}
Precharge (ϕ=0\phi=0) HIGH (VDDV_{DD}) LOW (0)
Evaluate (ϕ=1\phi=1) stays HIGH or falls to 0 stays LOW or rises to 1

So during evaluation, YY starts LOW and can only ever rise (0→1) — never fall. This is called a monotonically rising signal.


HOW to build one — worked construction

Goal: build a domino AND-gate Y = A·B.

  1. Pick the function for the PDN. A domino output is Y=XY=\overline{X}, and XX goes LOW (so YY goes HIGH) when the PDN conducts. We want Y=ABY=A\cdot B, so the PDN must conduct when AB=1A\cdot B=1. Why this step? The dynamic node computes the complement at XX; the inverter un-complements it, so PDN logic directly matches the non-inverted output.
  2. PDN = series NMOS for AND. Two NMOS AA then BB in series between XX and the evaluate transistor. Why? Series NMOS conduct only when both are on = logical AND.
  3. Add clocked precharge PMOS from VDDV_{DD} to XX, gate = ϕ\phi. Why? Sets XX HIGH ⇒ YY LOW during precharge (the required monotonic start).
  4. Add clocked evaluate NMOS at the bottom, gate = ϕ\phi. Why? Blocks any discharge during precharge so XX charges cleanly.
  5. Add static inverter XYX\to Y. Why? Provides drive, restores levels, and produces the monotonic non-inverting output for cascading.

The big limitation


Recall Feynman: explain to a 12-year-old

Imagine a row of dominoes standing up. You (the clock) first stand them all up — that's precharge. Then you tip the first one — evaluate. Each domino can only fall (go from up to down), never jump back up on its own. Because they only fall in one direction, one after another, they never knock each other over by accident. In the circuit, "standing up" = output is LOW, "fallen" = output rose to HIGH, and this one-way behavior lets us chain the gates safely and quickly.


Flashcards

Why can't plain dynamic gates be directly cascaded?
During evaluate their outputs start HIGH, so a downstream gate can discharge falsely before the upstream one finishes — a non-monotonic race.
What single element turns a dynamic gate into a domino gate?
A static CMOS inverter on the dynamic output node.
What is the state of a domino output right after precharge?
LOW (0), because the dynamic node is HIGH and the inverter negates it.
What key property makes domino cascadable?
Its output is monotonically rising during evaluate (starts LOW, can only go 0→1).
What is the fundamental limitation of domino logic?
It is non-inverting only — cannot produce an inverting function directly.
Why does a floating dynamic node hold its value?
No conducting path means dQ/dt=0, so Q and hence V=Q/C stay constant.
What is charge sharing and its fix?
Charge redistributing from X to internal PDN node caps drops V_X; fixed with a weak keeper PMOS.
Charge-sharing final voltage of node X (cap C_X at Vdd) with internal node (cap C_a at 0)?
V = C_X·Vdd/(C_X+C_a).
For a domino AND gate Y=A·B, how is the PDN arranged?
Two NMOS (A and B) in series, since output is non-inverting and PDN conducts for A·B=1.
Role of the keeper PMOS?
Weak PMOS (gate=Y) that trickle-charges X to fight leakage/charge-sharing while X should stay high.

Connections

  • Dynamic CMOS Logic — the precharge/evaluate base that domino builds on
  • Static CMOS Logic — the inverter used, and the fallback for inverting functions
  • Charge Sharing and Keepers — the reliability problem and cure
  • Clocking and Precharge Schemes — timing of ϕ\phi
  • NP / Zipper Domino — variants that overcome the non-inverting limit
  • Pull-Down Network Design — mapping Boolean functions to NMOS networks

Concept Map

fast but

fixed by

plus

forms

precharge sets HIGH

inverted by INV

floating when PDN off

starts LOW rises 0 to 1

keeps downstream PDN OFF

enables safe

Dynamic gate

Cascade race error

Domino gate

Static CMOS inverter

Dynamic node X

Output Y equals NOT X

Monotonically rising output

Node holds charge

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, dynamic logic bahut fast aur chhoti hoti hai kyunki usme clock ke do phase hote hain: precharge me node upar (HIGH) charge ho jaata hai, aur evaluate me agar pull-down network ON ho to node discharge ho jaata hai. Problem ye hai ki agar aap ek dynamic gate ka output seedha doosre dynamic gate me daalo, to evaluate ke shuru me sabhi outputs HIGH hote hain — isse downstream gate galat discharge ho jaata hai. Ye ek race condition hai aur dynamic node ka charge wapas nahi aata, to answer galat aa jaata hai.

Domino logic is problem ka jugaad hai: dynamic gate ke output pe ek chhota static inverter laga do. Ab actual output Y=XY=\overline{X} ho gaya. Precharge me XX HIGH tha, to YY LOW hoga. Evaluate me YY ya to LOW rahega ya 0 se 1 ki taraf badhega — kabhi girega nahi. Isko monotonically rising kehte hain. Bilkul dominoes ki tarah — ek girta hai tabhi agla girta hai, koi galti se dusre ko nahi giraata. Isliye ab gates ko safely cascade kar sakte ho.

Ek important limitation yaad rakhna: domino output hamesha non-inverting hota hai, isliye seedhe domino chain se inverting function (NAND/NOR jaisa) nahi ban sakta. Uske liye dual-rail ya doosre tricks use karte hain. Aur ek practical dikkat hai charge sharing — jab XX ka charge andar wale PDN nodes ke saath baant jaata hai to VXV_X gir jaata hai, jisse YY galat ho sakta hai; iska ilaaj hai ek chhota keeper PMOS jo XX ko thoda-thoda charge deta rehta hai. Bas itna samajh lo aur domino clear ho jaayega.

Go deeper — visual, from zero

Test yourself — CMOS Circuit Design

Connections