Domino logic: Visual walkthrough — Hardware deep dive

Step 1 — What a "node" and its "charge" even are

WHAT. A node is just a wire — a piece of metal where signals meet. Because it is metal near other metal, it behaves like a tiny bucket that stores electric charge. We call that storage its capacitance $C_{X}$ , and the amount of charge sitting in it $Q$ . The two connect by one rule:

$Q = C_{X} V_{X}$

$Q$ ::: how much electric charge is parked on the node (in coulombs).
$C_{X}$ ::: the "bucket size" of the node — how much charge it holds per volt.
$V_{X}$ ::: the voltage on the node — think "how full the bucket is."

WHY start here. Dynamic logic remembers a value by leaving charge sitting on a wire. To understand why the value can be lost (the whole danger), we must first see the wire as a bucket. Nothing else in this page makes sense without it.

PICTURE. The node $X$ is drawn as a bucket. Voltage $V_{X}$ = water level; charge $Q$ = water inside.

Step 2 — Why a floating node freezes its value

WHAT. If no wire lets charge flow in or out, the node is floating. The current $I$ (the flow of charge per second) is then exactly zero:

$I = \frac{d Q}{d t} = 0 \Rightarrow Q = constant \Rightarrow V_{X} = \frac{Q}{C _{X}} = constant$

$\frac{d Q}{d t}$ ::: the rate at which charge changes — how fast the bucket fills or drains.
$I$ ::: current, the same thing, given its circuit name.
setting it to $0$ ::: says "no pipe is open," so the water level cannot move.

WHY this tool (the derivative). We use $\frac{d Q}{d t}$ because "does the stored value change?" is literally a question about rate of change over time — and the derivative is the one tool built to answer exactly that. No conducting path ⇒ zero rate ⇒ frozen level.

PICTURE. A sealed bucket: both pipes shut, water level pinned. This is why a dynamic node can hold HIGH — and also why a wrong drain is unrecoverable.

Step 3 — The two phases of the clock $ϕ$

WHAT. A single control wire — the clock $ϕ$ — swings between two values, and each value opens a different pipe:

$ϕ$	Name	Top pipe (PMOS)	Bottom pipe (evaluate NMOS)
$0$	Precharge	OPEN → fills $X$ to $V_{D D}$	SHUT
$1$	Evaluate	SHUT	OPEN → $X$ may drain

$ϕ$ ::: the clock signal, the referee that says "now fill" or "now decide."
$V_{D D}$ ::: the supply voltage — the "full bucket" level, our logic HIGH.

WHY. A dynamic gate cannot both fill and decide at once, or it would fight itself. Splitting time into fill-then-decide is the whole trick, and $ϕ$ is the switch that does the splitting. See Clocking and Precharge Schemes for the timing.

PICTURE. Same bucket, two snapshots side by side: $ϕ = 0$ (top pipe open, filling) and $ϕ = 1$ (bottom pipe open, maybe draining).

Step 4 — The bare dynamic gate: node $X$ across a full cycle

WHAT. Put the pull-down network (PDN) — the stack of NMOS switches that "asks the question" — on the bottom pipe. Trace $X$ :

Precharge: $X$ climbs to $V_{D D}$ (HIGH), guaranteed.
Evaluate, PDN conducts: bottom pipe opens and the PDN drains $X$ to $0$ (LOW).
Evaluate, PDN blocked: node floats (Step 2) → $X$ stays HIGH.

WHY. This is the raw Dynamic CMOS Logic gate. Notice the danger already: during evaluate, $X$ begins HIGH. If we fed this raw $X$ into another gate, the downstream gate sees HIGH too early. Hold that thought.

PICTURE. A timeline of $V_{X}$ : flat-high through precharge, then at evaluate either a red fall to 0 or a blue flat line staying high.

Step 5 — Bolt on the inverter → the domino output $Y$

WHAT. Attach a static CMOS inverter to $X$ . Its job: output the opposite of its input.

$Y = \overline{X}$

$Y$ ::: the usable output of the domino gate — the wire we hand to the next gate.
$\overline{X}$ ::: "NOT $X$ ": HIGH when $X$ is LOW, LOW when $X$ is HIGH.

Now re-read the levels through the inverter:

Phase	$X$	$Y = \overline{X}$
Precharge	HIGH	LOW
Evaluate	HIGH or falls to 0	LOW or rises to 1

WHY the inverter and not just a buffer. Two reasons at once. (1) It flips the "starts HIGH" danger into "starts LOW." (2) It gives real drive strength to push the next gate. The flip is the star — see Step 6.

PICTURE. $X$ 's waveform on the left, inverter in the middle, $Y$ 's mirror-image waveform on the right — where $X$ falls, $Y$ rises.

Step 6 — The central result: $Y$ is monotonically rising

WHAT. During evaluate, $Y$ starts at $0$ and the only move it can make is $0 \to 1$ . It can never fall inside an evaluate phase. A signal that can only go up is called monotonically rising.

Why can't it fall? Because $Y$ falling would need $X$ to rise during evaluate — but during evaluate the top pipe is SHUT (Step 3), so $X$ has no way to refill. $X$ can only stay or fall ⇒ $Y$ can only stay or rise. $■$

WHY this is the whole point. Feed such a $Y$ into a downstream PDN transistor. That transistor's gate starts LOW ⇒ it starts OFF ⇒ the downstream node cannot drain early. It drains only after an upstream $Y$ climbs 0→1 — i.e. only after the previous "domino" has fallen. The race is structurally impossible.

PICTURE. A single evaluate window with $Y$ shown as: the only allowed transition is a green up-arrow; a red down-arrow is crossed out.

Step 7 — Cascade proof: two gates never fight

WHAT. Gate 1's output $Y_{1}$ drives a transistor in Gate 2's PDN.

At evaluate start: $Y_{1} = 0$ (from precharge) ⇒ Gate 2's transistor OFF ⇒ Gate 2's node safe.
Later: if the logic demands it, $Y_{1}$ rises $0 \to 1$ ⇒ Gate 2's transistor turns ON exactly once, in the right order ⇒ Gate 2 evaluates correctly.

WHY. This is Step 6 applied twice. The monotonic rule guarantees an ordering: nothing downstream moves until its upstream input has finished. Dominoes fall left to right, never backward.

PICTURE. Two gate boxes chained; timeline shows $Y_{1}$ rising first, then $Y_{2}$ rising after — like two dominoes toppling in sequence.

WHAT. The PDN's internal wires are also buckets (call one $C_{a}$ , sitting at $0$ ). If evaluate opens a path from $X$ to that empty bucket but not all the way to ground, charge splits between them. Conserve charge:

$V_{f ina l} = \frac{C _{X} V _{D D} + C _{a} \cdot 0}{C _{X} + C _{a}} = \frac{C _{X} V _{D D}}{C _{X} + C _{a}}$

$C_{X} V_{D D}$ ::: all the charge originally on $X$ (the only charge in the system).
$C_{a} \cdot 0$ ::: the empty internal bucket contributes nothing.
$C_{X} + C_{a}$ ::: the two buckets now share one common level, so add their sizes.

The drop $Δ V = V_{D D} \frac{C _{a}}{C _{X} + C _{a}}$ . If it pushes $X$ below the inverter's switching point, $Y$ falsely rises — breaking monotonicity for the wrong reason.

WHY show this. A derivation that only shows the happy path is a lie. This edge case is real, and its cure — a weak keeper PMOS (gate $= Y$ ) that trickle-refills $X$ — is why Charge Sharing and Keepers exists. The keeper fights $Δ V$ so $X$ stays HIGH when it should.

PICTURE. Big bucket $X$ (full) connected to small empty bucket $C_{a}$ ; water levels out to $V_{f ina l}$ ; a small tap (keeper) drips $X$ back up.

The one-picture summary

Everything above, compressed: precharge fills $X$ (so $Y = 0$ ), evaluate either drains $X$ (so $Y$ rises) or holds it — and because the top pipe is shut during evaluate, $Y$ can only rise, which lets dominoes chain safely.

Recall Feynman: the whole walkthrough in plain words

A wire is a bucket; how full it is = its voltage; how much water = its charge. Seal the bucket and the level can't change — that's how a chip "remembers" a bit. A clock opens one of two pipes: first a top pipe fills the bucket (precharge), then a bottom pipe lets it maybe drain (evaluate). We slap an inverter on the bucket, so "full bucket" reads out as 0 and "empty bucket" reads out as 1. Because the top pipe is shut during evaluate, the bucket can only stay full or drain — never refill — so the readout can only stay 0 or climb to 1, never fall. Every gate's output starts at 0 and only ever rises. Wire them in a row and each one waits for the one before it to "fall" before it moves — a chain of dominoes that can only topple forward, so they never knock each other over by mistake. The one wrinkle: tiny hidden buckets inside the gate can steal some water when the pipe opens, lowering the level enough to fool the inverter — so we add a slow dripping tap (the keeper) to top it back up.

Connections

Domino logic (index 3.2.12) — the parent this walkthrough derives
Dynamic CMOS Logic — the precharge/evaluate base (Steps 3–4)
Static CMOS Logic — the inverter bolted on (Step 5)
Charge Sharing and Keepers — the degenerate case (Step 8)
Clocking and Precharge Schemes — timing of $ϕ$
Pull-Down Network Design — the NMOS network that "asks the question"
NP / Zipper Domino — variants that beat the non-inverting limit