Domino logic: Foundations — Hardware deep dive

Before you can trust that sentence, you must be able to read every piece of it. This page builds every symbol the parent note uses, from absolute zero, in an order where each idea rests on the one before it.

0. What is a voltage, and what do HIGH / LOW mean?

Why the topic needs it. Every phrase in the parent — " $X$ sits HIGH", " $Y$ starts LOW", "output rises 0→1" — is a statement about where a wire sits on this ruler. Without the ruler, none of those sentences mean anything.

$V_{D D}$ ::: the supply voltage; the HIGH level; logic 1.
$0$ / ground ::: the LOW level; logic 0.

1. Charge $Q$ and capacitance $C$ — where the "memory" lives

Picture: a water bucket. $C$ = how wide it is, $V$ = how high the water stands, $Q$ = total water. Fill it up ( $V = V_{D D}$ ) and — if there's no hole — it stays full.

Why the topic needs it. The dynamic node $X$ is exactly a bucket. "Precharge" = fill the bucket. "The node holds its value" = the bucket has no hole so the water stays put. The whole fragility of dynamic logic is: this bucket has no pump refilling it, so any leak matters.

2. Current $I$ — and why a floating node freezes

$I$ ::: current, the flow rate of charge.
$\frac{d Q}{d t} = 0$ ::: charge isn't changing, so the node is frozen (floating).

3. The transistor as a switch — NMOS and PMOS

Picture: two light-switches. The NMOS switch has a "turn ON at 1" label; the PMOS has a "turn ON at 0" label (a little bubble on the gate to remind you it's inverted). The bubble is the visual code for "opposite."

Why the topic needs it. Every box in a domino gate is one of these two switches:

the precharge PMOS (fills the bucket when the clock is 0),
the evaluate NMOS (opens the drain at the bottom when the clock is 1),
the pull-down network made of NMOS,
the two transistors inside the inverter.

4. The clock $ϕ$ and its two phases

Why the topic needs it. "During precharge" and "during evaluate" in the parent are just "while $ϕ = 0$ " and "while $ϕ = 1$ ." The clock is the referee that guarantees the fill-then-decide order, and this ordering is what makes the answer trustworthy. See Clocking and Precharge Schemes for how $ϕ$ is timed.

$ϕ = 0$ ::: precharge phase — buckets get filled, no discharge allowed.
$ϕ = 1$ ::: evaluate phase — the gate decides to hold or dump.

5. The dynamic node $X$ and the output $Y$

Picture: a timeline over one clock beat. Top track = $X$ : starts HIGH during precharge, then during evaluate it either stays high or falls to 0. Bottom track = $Y = \overline{X}$ : the mirror image — starts LOW, then either stays low or rises to 1. The arrow on $Y$ points only upward during evaluate: this is the monotonically rising property, and it is the reason the whole scheme is called domino.

$X$ ::: internal dynamic node; precharged HIGH; holds the complement.
$Y = \overline{X}$ ::: usable output; NOT of $X$ ; starts LOW and can only rise during evaluate.
$\overline{X}$ / the bar ::: logical NOT (opposite level).

6. Series NMOS = AND, and the pull-down network (PDN)

Why the topic needs it. The worked AND gate Y = A·B uses two NMOS in series precisely because "both inputs 1" must be the only case that drains $X$ (making $Y$ rise to 1). Mapping any Boolean function to such a network is Pull-Down Network Design.

Prerequisite map

Read it bottom-up: everything above feeds Dynamic CMOS Logic, and the dynamic gate plus the inverting output $Y = \overline{X}$ produce Domino logic (the parent, see also the Hinglish note).

Equipment checklist

Test yourself — you should be able to fill each blank instantly before reading the parent.

What do HIGH and LOW mean as voltages? ::: HIGH = $V_{D D}$ = logic 1; LOW = $0$ V = ground = logic 0.
Write the one rule linking charge, capacitance and voltage. ::: $Q = C V$ , so $V = Q / C$ .
Why does a floating node keep its voltage? ::: No path means $I = d Q / d t = 0$ , so $Q$ and hence $V = Q / C$ never change.
When does an NMOS conduct? A PMOS? ::: NMOS conducts when its gate is HIGH (1); PMOS conducts when its gate is LOW (0).
What is the clock $ϕ$ and its two phases? ::: A ticking 0/1 signal; $ϕ = 0$ = precharge (fill), $ϕ = 1$ = evaluate (decide).
What does $\overline{X}$ mean and who computes it in a domino gate? ::: NOT $X$ (opposite level); the static inverter computes it as $Y$ .
Why must the output be $Y = \overline{X}$ instead of $X$ ? ::: So $Y$ starts LOW and can only rise (monotonic), preventing downstream false discharge.
What logic do two NMOS in series compute, and why? ::: AND — the chain conducts only when both switches are closed (both inputs HIGH).