Domino logic: Worked examples — Hardware deep dive

This page is the drill room for Domino logic. The parent note told you the rules; here we run the machine through every situation it can face — every clock phase, every input pattern, the tricky charge-sharing numbers, a cascade timing puzzle, and an exam-style trap.

Before the examples, we lay out a map of all cases so you can see nothing is skipped.

The scenario matrix

Domino logic has a small number of "levers." Every worked example below flips one of them. Here is the full set:

Cell	Lever being tested	What could go wrong / be interesting
A. Precharge phase	$ϕ = 0$	Node $X$ must reach $V_{D D}$ , output $Y$ must be LOW regardless of data inputs
B. Evaluate, PDN conducts	$ϕ = 1$ , function TRUE	$X$ falls to 0, $Y$ rises 0→1
C. Evaluate, PDN off	$ϕ = 1$ , function FALSE	$X$ holds HIGH (floating), $Y$ stays LOW
D. Degenerate input	one input = 0 in a series AND	partial path — must NOT discharge
E. Charge sharing (numeric)	internal node caps	$V_{X}$ drops; does it cross the inverter trip point?
F. Keeper rescue (numeric)	weak PMOS added	keeper current vs. leakage — does $X$ survive?
G. Cascade timing	Gate1 → Gate2	monotonic 0→1 makes ordering safe
H. The inverting trap	build a NAND at the output	domino is non-inverting — this is impossible directly
I. Limiting case	$C_{a} \to 0$ and $C_{a} \to \infty$	charge sharing vanishes / collapses

The examples below hit every cell A–I (Cell E has a safe subcase and a danger variant; both are labelled).

Worked example Cell A — Precharge ignores the data

Statement. A domino AND gate Y = A·B is in precharge ( $ϕ = 0$ ). Someone sets $A = 1, B = 1$ . What are $X$ and $Y$ ?

Forecast: guess $X$ and $Y$ before reading.

Evaluate NMOS is OFF because its gate is $ϕ = 0$ . Why this step? An NMOS conducts only on a HIGH gate; here the gate is $ϕ = 0$ (LOW), so it is OFF and blocks any path to ground. The PDN's state is therefore irrelevant — even a fully-on $A = B = 1$ path leads nowhere.
Precharge PMOS is ON. It pulls $X$ up to $V_{D D}$ . Why this step? A PMOS conducts on a LOW gate (opposite of an NMOS). Its gate is $ϕ = 0$ (LOW), so it turns ON and connects $V_{D D}$ to $X$ .
Inverter negates: $Y = \overline{X} = \overline{1} = 0$ .

Answer: $X = V_{D D}$ (HIGH), $Y = 0$ (LOW).

Verify: This is exactly the required monotonic start — $Y$ LOW no matter the data. Sanity check: the whole point of precharge is that data is ignored, so $A = B = 1$ changing nothing confirms correct behaviour. See Clocking and Precharge Schemes.

Worked example Cell B — Evaluate with the function TRUE

Statement. Same gate, now $ϕ = 1$ , and $A = 1, B = 1$ . Find $X$ , then $Y$ .

Forecast: which way does $Y$ move?

Precharge PMOS OFF. No more pull-up. Why this step? A PMOS conducts only on a LOW gate; now the gate is $ϕ = 1$ (HIGH), so it turns OFF and disconnects $V_{D D}$ from $X$ .
Evaluate NMOS ON. A path to ground is now allowed. Why this step? An NMOS conducts on a HIGH gate; its gate is $ϕ = 1$ (HIGH), so it turns ON and opens the bottom of the discharge path.
Series PDN conducts: $A$ -NMOS on and $B$ -NMOS on ⇒ complete path $X \to$ ground. Why this step? Two NMOS in series = AND. Both on is the only way current flows — see Pull-Down Network Design.
$X$ discharges to 0, so $Y = \overline{0} = 1$ .

Answer: $X = 0$ , $Y = 1$ . Since $Y$ began at 0 (from precharge) and ended at 1, it rose 0→1 — monotonic.

Verify: $Y = A \cdot B = 1 \cdot 1 = 1$ . ✓ Matches the intended AND function.

Worked example Cell C — Evaluate with the function FALSE (the floating hold)

Statement. Same gate, $ϕ = 1$ , but $A = 1, B = 0$ . Find $X$ and $Y$ , and explain what physically holds $X$ .

Forecast: does $X$ stay at $V_{D D}$ exactly, or leak?

Precharge PMOS OFF, evaluate NMOS ON (as in Cell B). Why this step? Same gate-level rules: with $ϕ = 1$ (HIGH) the PMOS is OFF (PMOS wants a LOW gate) and the evaluate NMOS is ON (NMOS wants a HIGH gate).
PDN does NOT conduct: $B = 0$ turns the $B$ -NMOS OFF, breaking the series chain. Why this step? One open switch in a series chain opens the whole chain — no ground path.
$X$ is now floating — no pull-up (PMOS off), no pull-down (PDN off). Why this step? "Floating" means $X$ has no conducting connection to either supply rail, so nothing can push charge in or out. Look at the figure above: the red node has no arrow in or out.
Charge conservation holds $X$ : with no path, current $I = 0$ , so $\frac{d Q}{d t} = I = 0$ and $Q$ is constant; hence $V_{X} = \frac{Q}{C _{X}} = V_{D D}$ (ideally). Thus $Y = \overline{1} = 0$ . Why this step? Charge only moves as current; zero current means the stored charge cannot change, and a fixed charge on a fixed capacitance means a fixed voltage.

Answer: $X = V_{D D}$ (held), $Y = 0$ .

Verify: $Y = A \cdot B = 1 \cdot 0 = 0$ . ✓ And note this is the fragile state — leakage and charge sharing attack it (Cells E, F). See Dynamic CMOS Logic.

Worked example Cell E (safe subcase) — Charge sharing, numeric (does the output flip falsely?)

Statement. Take Cell D's held-HIGH scenario, but now be realistic: node $X$ has $C_{X} = 30 fF$ at $V_{D D} = 1.0 V$ . Between the two series NMOS sits an internal node $a$ with $C_{a} = 20 fF$ , sitting at $0 V$ (it discharged last cycle). With $A = 0, B = 1$ : the $B$ transistor being ON connects $X$ 's region to node $a$ . Find the shared voltage $V_{f ina l}$ and decide if $Y$ falsely flips, given the inverter trips at $V_{t r i p} = 0.5 V$ .

Forecast: guess $V_{f ina l}$ — above or below 0.5 V?

Charge before (conserved quantity): $Q = C_{X} V_{D D} + C_{a} (0) = 30 fF \times 1.0 V = 30 fC$ . Why this step? An isolated set of capacitors conserves total charge — the only law that survives when there is no external path.
Total capacitance after they connect: $C_{X} + C_{a} = 30 + 20 = 50 fF$ . Why this step? When two capacitors are wired to the same node they act as one combined capacitor of value $C_{X} + C_{a}$ ; the shared charge spreads over this total.
Common voltage: $V_{f ina l} = \frac{C _{X} V _{D D}}{C _{X} + C _{a}} = \frac{30}{50} (1.0) = 0.6 V$ . Why this step? The conserved charge from step 1 now sits on the combined capacitance from step 2; voltage is charge divided by capacitance, $V = Q / C$ , so this ratio is the settled node voltage.
Compare to trip: $0.6 V > 0.5 V$ , so the inverter still reads $X$ as HIGH ⇒ $Y$ stays 0. No false flip — this time. Why this step? The inverter decides HIGH vs LOW by comparing its input to the trip point $V_{t r i p}$ ; anything above $V_{t r i p}$ is still interpreted as HIGH, so the output is safe only if $V_{f ina l}$ clears that bar.

Answer: $V_{f ina l} = 0.6 V$ ; $Y$ correctly stays LOW.

Verify: Drop $Δ V = V_{D D} \frac{C _{a}}{C _{X} + C _{a}} = 1.0 \times \frac{20}{50} = 0.4 V$ , and $1.0 - 0.4 = 0.6$ . ✓ Consistent. See Charge Sharing and Keepers.

Worked example Cell E (danger variant) — when charge sharing DOES flip the output

Statement. Same as the safe subcase but the internal node is fatter: $C_{a} = 40 fF$ (still $C_{X} = 30$ , $V_{D D} = 1.0$ , $V_{t r i p} = 0.5$ ). Now what happens?

Forecast: bigger $C_{a}$ — better or worse?

Charge before: $Q = C_{X} V_{D D} + C_{a} (0) = 30 fC$ (unchanged, $C_{a}$ started at 0 V). Why this step? Same conservation law as the safe subcase — total charge is fixed, and the internal node contributes nothing because it began at 0 V.
Total capacitance after they connect: $C_{X} + C_{a} = 30 + 40 = 70 fF$ . Why this step? The two capacitors again merge into one combined $C_{X} + C_{a}$ ; the same 30 fC now spreads over a bigger total, so the voltage must drop further.
$V_{f ina l} = \frac{30}{70} (1.0) = \frac{30}{70} \approx 0.4286 V$ . Why this step? Again $V = Q / C$ : the fixed 30 fC over the larger 70 fF gives a lower settled voltage than the safe subcase.
Compare: $0.4286 < 0.5$ ⇒ inverter reads $X$ as LOW ⇒ $Y$ falsely rises to 1. A wrong answer that can't be undone. Why this step? Now $V_{f ina l}$ has fallen below the trip point, so the inverter misreads the still-"supposed-to-be-HIGH" node as LOW and flips the output — exactly the failure the keeper prevents (next example).

Answer: $V_{f ina l} \approx 0.429 V$ ; false output $Y = 1$ .

Verify: $Δ V = 1.0 \times \frac{40}{70} \approx 0.571 V$ , and $1.0 - 0.571 = 0.429$ . ✓ Bigger internal cap ⇒ bigger drop ⇒ more danger.

The plot below traces $V_{f ina l}$ across all internal-node sizes at once, marking both the safe ( $C_{a} = 20$ ) and dangerous ( $C_{a} = 40$ ) cases above so you can see them on one curve — it is the geometric summary of Cells E and I.

The red curve falls as $C_{a}$ grows: the safe dot ( $0.60$ V) sits above the dashed trip line, the dangerous dot ( $0.43$ V) sits below it. Everything left of where the curve crosses $0.5$ V is safe; everything right of it flips falsely.

Worked example Cell F — Keeper to the rescue (numeric current balance)

Statement. In a held-HIGH gate, leakage tries to drain $X$ at $I_{l e ak} = 5 nA$ . A weak keeper PMOS (gate tied to $Y$ , which is LOW when $X$ is HIGH, so the keeper is ON) supplies $I_{k ee p} = 20 nA$ . Over one evaluate window of $T = 2 ns$ , does $X$ ( $C_{X} = 30 fF$ , at $1.0$ V) stay above $V_{t r i p} = 0.5$ V?

Forecast: net current in or out of $X$ ?

Net current at node $X$ : $I_{n e t} = I_{k ee p} - I_{l e ak} = 20 - 5 = 15 nA$ into $X$ . Why this step? Keeper pushes charge in, leakage pulls it out; only the difference moves the node.
Since $I_{n e t} > 0$ , $X$ is being refilled, not drained — it cannot fall below $V_{D D}$ due to leakage. Voltage change over the window: $Δ V = \frac{I _{n e t} T}{C _{X}} = \frac{15 nA \times 2 ns}{30 fF}$ .
Compute: $15 \times 1 0^{- 9} \times 2 \times 1 0^{- 9} = 3 \times 1 0^{- 17} C$ ; divide by $30 \times 1 0^{- 15} F$ : $Δ V = 2 \times 1 0^{- 3} V = 2 mV$ (upward, clamped at $V_{D D}$ ).

Answer: $X$ stays essentially at $V_{D D} (\geq 0.998 V) ≫ 0.5 V$ . Output safe.

Verify: Net current positive ⇒ node rises, never crosses $0.5$ V. The keeper wins because $I_{k ee p} > I_{l e ak}$ . If instead $I_{k ee p} < I_{l e ak}$ , $X$ would slowly droop — the keeper must out-drive leakage but stay weak enough not to fight a real pull-down. See Charge Sharing and Keepers.

Worked example Cell G — Cascade timing (why monotonic ordering is safe)

Statement. Gate1 (Y1 = A·B) feeds its output $Y_{1}$ into Gate2's PDN. All share clock $ϕ$ . Inputs $A = B = 1$ . Walk the timeline and prove Gate2 never falsely discharges.

Forecast: at the instant evaluate begins, is $Y_{1}$ high or low?

End of precharge: every domino output is LOW, so $Y_{1} = 0$ . Why this step? Cell A already proved outputs are LOW after precharge regardless of data.
Evaluate begins ( $ϕ : 0 \to 1$ ): Gate2's input transistor (driven by $Y_{1} = 0$ ) is OFF. Gate2's node cannot discharge yet — no race. Why this step? That input transistor is an NMOS, and an NMOS conducts only when its gate is HIGH. Its gate is $Y_{1} = 0$ (LOW), so it is OFF and opens Gate2's discharge chain — with the chain open, Gate2's node has no path to ground and simply cannot lose charge at this instant, no matter what else evaluates.
Gate1 finishes: its $X_{1}$ falls, $Y_{1}$ rises $0 \to 1$ (Cell B).
Only now does Gate2's transistor turn ON and Gate2 evaluates. The 0→1-only rule guaranteed the correct order.

Answer: No false discharge — dominoes fall forward in order. Because $Y_{1}$ only ever steps up (0→1), Gate2 always waits for it.

Verify: The safety relies entirely on $Y_{1}$ being monotonically rising. A hypothetical non-monotonic $Y_{1}$ (starting HIGH) would violate step 2 — which is precisely why plain Dynamic CMOS Logic can't cascade.

Worked example Cell H — The inverting trap (an impossible request)

Statement. Exam twist. "Build a single domino gate whose output is Y = NAND(A,B) = ¬(A·B)." Show why this can't be done directly, and what you'd do instead.

Forecast: feels doable — just tweak the PDN?

Recall the monotonic constraint: a domino output starts LOW at evaluate and can only rise 0→1.
A NAND is HIGH when $A \cdot B = 0$ , i.e. HIGH for the input $A = B = 0$ at the very start of evaluate. But the output is forced LOW at evaluate start. Contradiction — the required value (1) cannot appear because the output can't start high. Why this step? The output's starting value is not free — precharge fixes it at 0. Any function that needs a HIGH-at-start output is unbuildable in pure domino.
The escape: use dual-rail domino (compute both $Y$ and $\overline{Y}$ on two monotonic rails) or push the inversion into a following Static CMOS Logic stage — or use a zipper/NP scheme (alternating N-type and P-type dynamic stages so that each stage's output feeds the opposite type, allowing effective inversion between stages; see NP / Zipper Domino). Why this step? Each of these adds a genuine source of inversion that pure single-rail domino lacks, working around the monotonic constraint rather than violating it.

Answer: Impossible as a single domino gate. Domino is non-inverting logic only — inversion must come from dual-rail, a static stage, or an NP/zipper structure.

Verify: Truth-table check — for $A = B = 0$ : NAND wants $Y = 1$ , but domino output at evaluate start $= 0$ ; it can rise but is never pre-set high, so the "no-discharge" case yields $Y = 0 \neq = 1$ . Contradiction confirmed.

Worked example Cell I — Limiting cases of charge sharing

Statement. In $V_{f ina l} = \frac{C _{X} V _{D D}}{C _{X} + C _{a}}$ , examine the two extremes $C_{a} \to 0$ and $C_{a} \to \infty$ . What do they mean physically? (These are the two ends of the red curve in the figure above.)

Forecast: which extreme is safe, which is fatal?

$C_{a} \to 0$ (a tiny/nonexistent internal node): $V_{f ina l} \to \frac{C _{X} V _{D D}}{C _{X} + 0} = V_{D D}$ . Why this step? If there is no internal capacitance to soak up charge, none of $X$ 's charge leaves — the formula reduces to $C_{X} V_{D D} / C_{X} = V_{D D}$ . This is the ideal held-HIGH of Cell C. Safe.
$C_{a} \to \infty$ (a huge internal node): $V_{f ina l} \to \frac{C _{X} V _{D D}}{\infty} \to 0$ . Why this step? An enormous internal capacitance dominates the denominator, so the same fixed charge spreads to near-zero voltage — $X$ is effectively fully drained. Guaranteed false flip. Worst case.
In between, $V_{f ina l}$ slides monotonically from $V_{D D}$ down to $0$ as $C_{a}$ grows — matching Cell E (safe, $C_{a} = 20$ ) and its danger variant ( $C_{a} = 40$ ). Why this step? The curve in the figure is monotone decreasing, so the two numeric cases sit exactly on the ends' path — no surprises between them.

Answer: $C_{a} \to 0 \Rightarrow V_{f ina l} = V_{D D}$ (safe); $C_{a} \to \infty \Rightarrow V_{f ina l} = 0$ (fatal). Real designs keep $C_{a} ≪ C_{X}$ and add a keeper.

Verify: With $V_{D D} = 1.0$ : at $C_{a} = 0$ , $V_{f ina l} = 1.0$ ; as $C_{a}$ grows, e.g. $C_{a} = C_{X} = 30$ gives $V_{f ina l} = 0.5$ (right on the trip point). ✓ The formula is monotone decreasing in $C_{a}$ .

Recall Self-test: name the cell

A domino gate is in precharge with $A = B = 1$ ; output $Y$ ? ::: LOW — precharge ignores data (Cell A). $ϕ = 1$ , only one series input high; does $X$ discharge? ::: No — one open switch breaks the series chain (Cell D). $C_{X} = 30$ fF at 1 V shares with $C_{a} = 20$ fF at 0 V; $V_{f ina l}$ ? ::: $0.6$ V (Cell E safe subcase). Same but $C_{a} = 40$ fF; $V_{f ina l}$ and result? ::: $\approx 0.429$ V, false flip past a 0.5 V trip (Cell E danger variant). Keeper 20 nA vs leakage 5 nA — net effect on $X$ ? ::: Net $+ 15$ nA into $X$ , node stays HIGH (Cell F). Why can't a single domino gate output a NAND? ::: Output is forced LOW at evaluate start and can only rise; NAND needs HIGH-at-start (Cell H).

Connections

Domino logic — the parent this drill supports
Dynamic CMOS Logic — the precharge/evaluate base (Cells B, C, G)
Static CMOS Logic — the inverter and the inverting-function fallback (Cell H)
Charge Sharing and Keepers — Cells E, F, I
Clocking and Precharge Schemes — Cell A timing
NP / Zipper Domino — escaping the inverting limit (Cell H)
Pull-Down Network Design — series-AND mapping (Cells B, D)