Domino logic: Question bank — Hardware deep dive

Definition Symbols used on this page — read first

Every trap below uses these; none appears before it is defined here.

== $ϕ$ (the clock phase signal)== — a single square-wave signal that runs the gate. $ϕ = 0$ means precharge phase; $ϕ = 1$ means evaluate phase. It gates both the precharge PMOS and the evaluate NMOS.
PDN (Pull-Down Network) — the network of NMOS transistors (see Pull-Down Network Design) between the dynamic node $X$ and the evaluate transistor. It conducts a discharge path exactly when the Boolean function is true.
== $X$ == — the internal dynamic node (top of the PDN). == $Y = \overline{X}$ == — the gate's usable output, taken through the static inverter.
== $Q$ == — the electric charge stored on node $X$ 's capacitance $C_{X}$ . Because $Q = C_{X} V_{X}$ , the node's voltage is $V_{X} = Q / C_{X}$ .
== $C_{X}$ == — total parasitic capacitance at node $X$ . == $C_{a}$ == — the parasitic capacitance of an internal PDN node (a wire junction between two stacked NMOS, below $X$ ), which starts near $0 V$ and can steal charge from $X$ .

Look at the labelled circuit before starting — it names every device the questions refer to:

The monotonicity property (why $Y$ can only rise during evaluate) is derived visually here:

True or false — justify

A domino gate is just a dynamic gate with an extra inverter, so it is slower than plain dynamic logic.

False in the way that matters — the inverter adds a small delay but enables cascading and provides drive; the net design is faster than static CMOS while being safely chainable, which plain dynamic gates cannot do.

During evaluate, a domino output can go both HIGH→LOW and LOW→HIGH depending on inputs.

False — a domino output is monotonically rising: it starts LOW after precharge and can only stay LOW or rise 0→1 during evaluate. It never falls during evaluate.

The dynamic node

X

and the domino output

Y

move in the same direction during evaluate.

False — they are opposite:

X

starts HIGH and can only fall (or hold), while

Y = \overline{X}

starts LOW and can only rise (or hold). The inverter flips both level and direction.

You can build any Boolean function with a chain of domino gates alone.

False — every domino output is non-inverting (rises only), so no chain of pure domino gates can produce an inverting function like a plain NAND at the output; inversion needs dual-rail, reorganized logic, or a static gate.

A floating dynamic node loses its value the instant the PDN (pull-down network) turns off.

False — a floating node holds its value: with no conducting path the charge

Q

C_{X}

obeys

\frac{d Q}{d t} = 0

, so

Q

and thus

V_{X} = Q / C_{X}

stay put (ignoring slow leakage). That holding is exactly what dynamic logic relies on.

Charge sharing only concerns the top node

X

, since that's the only capacitor.

False — internal PDN nodes are also parasitic capacitors (their capacitance is

C_{a}

). When evaluate begins, charge on

X

can redistribute onto those internal caps, dropping

V_{X}

even when the PDN never fully conducts.

A keeper PMOS must be a strong, wide transistor to protect node

X

False — the keeper is deliberately weak. A strong keeper would fight the legitimate pull-down and slow (or block) a correct 1→0 discharge of

X

; it only needs to trickle-refill against leakage and charge sharing.

For a domino gate, the PDN is designed for the complement of the desired output.

False — because the inverter un-complements

X

, the PDN conducts directly for the desired non-inverted output. For

Y = A \cdot B

the PDN conducts when

A \cdot B = 1

(series NMOS), not for its complement.

Two domino gates in series can create a false race, just like two plain dynamic gates.

False — the race is cured: at evaluate start every domino output is LOW, keeping downstream PDN transistors OFF, so nothing discharges early. Discharge only happens after an upstream output rises — the whole point of monotonicity.

Spot the error

"I'll connect one dynamic gate's output straight to another dynamic gate's input to save the inverter."

The error: dynamic outputs sit HIGH during precharge, so the downstream gate sees a HIGH and discharges falsely at evaluate start — an unrecoverable race. The inverter (making a domino gate) is what forces the LOW-start needed to prevent this.

"My domino AND uses two NMOS in parallel between

X

and the evaluate transistor."

Parallel NMOS conduct when either input is high — that is an OR condition, giving

Y = A + B

. For AND you need them in series, so the path conducts only when both are high.

"I removed the evaluate NMOS to simplify — precharge still works."

Without the evaluate transistor, the PDN can pull

X

low during precharge whenever inputs are high, fighting the precharge PMOS and burning static current. The evaluate NMOS blocks any discharge path until

ϕ = 1

X

charges cleanly.

"To make an inverting domino, I just wired the PDN for the complement function."

The output is still taken through the inverter and still only rises — you cannot force a monotonically-falling (inverting) domino output no matter how you wire the PDN. You need a fundamentally different scheme like NP / Zipper Domino or dual-rail.

"Charge sharing dropped

V_{X}

a little, but

Y

is fine since

X

is still above 0."

The threat is the inverter's switching threshold, not 0. If

Δ V = V_{D D} \frac{C _{a}}{C _{X} + C _{a}}

(where

C_{a}

is the internal-node capacitance) pushes

V_{X}

below that threshold, the inverter flips and

Y

goes falsely HIGH — a wrong output.

"The keeper's gate connects to the clock

ϕ

The keeper's gate connects to the ==output

Y

==, not the clock. When

Y

is LOW (meaning

X

should stay HIGH) the keeper turns on to hold

X

up; once

Y

rises the keeper turns off so it doesn't fight the correct discharge.

"I'll size the keeper as wide as the PDN so

X

is well protected."

Wrong trade-off: the keeper must be weaker than the series PDN pull-down (rule of thumb: keeper current a small fraction, roughly a tenth, of PDN pull-down current) so a legitimate discharge wins a brief contention. Too strong and the correct 1→0 on

X

is blocked or badly slowed.

Why questions

Why does a monotonically rising output specifically prevent the cascade race?

A downstream PDN transistor driven by such a signal starts OFF (input LOW) and can only turn ON after the upstream gate legitimately rises. Discharge is therefore always ordered "upstream first" — dominoes fall one way, never backward.

Why, precisely, can

Y

only rise during evaluate (the monotonicity derivation)?

At evaluate start

X = V_{D D}

Y = 0

. The only device that can move

X

is the PDN, and it can only pull down (NMOS to ground) — there is no pull-up during evaluate (precharge PMOS is OFF). So

X

can only fall or hold, hence

Y = \overline{X}

can only rise or hold. The step-by-step charge picture is in the second figure.

Why is the dynamic node the complement of the logic result rather than the result itself?

The PDN discharges

X

(drives it LOW) when it conducts, so

X

naturally encodes NOT(function). The static inverter then restores the true function at

Y

, which is also what makes

Y

non-inverting.

Why does domino logic use fewer transistors than the equivalent static CMOS gate?

A static gate needs a full complementary pull-up PMOS network mirroring the PDN. Domino replaces that whole pull-up network with a single clocked precharge PMOS, so only the NMOS PDN plus a few clocked/inverter devices remain.

Why must the precharge phase drive

X

HIGH (making

Y

LOW) rather than the reverse?

The safe cascade rule requires every output to start at the value it can only leave in one direction. Starting

Y

LOW lets it only rise; that guaranteed LOW start is what keeps downstream PDN transistors OFF at evaluate begin.

Why can leakage alone corrupt a domino output even with no charge sharing?

When

X

floats HIGH during evaluate, small sub-threshold and junction leakage slowly bleed charge

Q

off

C_{X}

; since

V_{X} = Q / C_{X}

, that lowered charge can eventually cross the inverter threshold and flip

Y

. The keeper counters this.

Why does inserting a static inverter also help drive downstream loads?

The floating dynamic node

X

is weak and easily disturbed; the inverter's transistors actively source/sink current, giving a strong, level-restored output capable of driving the capacitance of the next gate's inputs.

Edge cases

If, during evaluate, the PDN never conducts (all-off inputs), what is

Y

and why?

X

stays HIGH (holds its precharged charge) so

Y

stays LOW. The output correctly reports "function = 0", held by stored charge rather than any active pull-up.

What happens to a domino output if the evaluate phase is stretched extremely long?

A held-HIGH

X

slowly leaks toward LOW over time, risking a false 0→1 on

Y

. This sets a maximum evaluate duration; the clocking scheme (and a keeper) must respect that limit.

What is the output state during the transition moment when

ϕ

switches 0→1 with all inputs LOW?

Precharge PMOS turns off and evaluate NMOS turns on, but with no PDN path

X

simply stays HIGH on its capacitance, so

Y

holds LOW. Nothing switches — the gate reports 0 with no glitch.

What happens at the falling edge

ϕ : 1 \to 0

(end of evaluate)?

Evaluate NMOS turns off (cutting any ground path) and the precharge PMOS turns on, forcing

X

back HIGH so

Y

resets to LOW — every gate is re-armed for the next cycle. Any computed result must have been captured downstream before this edge, because it is destroyed here.

In a multi-phase domino pipeline, why must successive stages precharge/evaluate in a staggered order?

A later stage must still be in evaluate (or already latched) while its driving stage's result is valid; if a stage precharges too early it wipes

X

(and

Y \to 0

) before the next stage read it. Phase ordering (see Clocking and Precharge Schemes, NP / Zipper Domino) guarantees each result is consumed before its producer resets.

Two domino gates share an input that arrives late, after evaluate has begun — is that safe?

A rising late input is safe because it only ever adds a discharge (monotonic). A late-arriving input that needs to fall would be a violation — inputs to a domino PDN must not fall during evaluate, or a wrongful early discharge already happened.

If a keeper is too weak to overcome leakage in a slow clock, what fails?

V_{X}

droops past the inverter threshold and

Y

falsely rises to 1, corrupting a "0" result. The cure is a slightly stronger keeper or a faster clock — a trade-off with the speed of the legitimate 1→0 discharge.

Can a domino gate with an empty PDN (no NMOS path at all) ever produce

Y = 1

No — with no discharge path

X

can never fall, so

Y

stays permanently LOW. Such a gate is a constant-0, useful only as a degenerate corner case, not real logic.

What if the precharge PMOS is too weak to fully charge

X

before evaluate?

X

starts evaluate below

V_{D D}

, so it is already closer to the inverter threshold and far more vulnerable to charge sharing/leakage flipping

Y

. Precharge must be sized to fully restore

X

within the precharge phase.

Connections

Domino logic (Hinglish) — the parent topic these traps drill
Dynamic CMOS Logic — the race these questions keep returning to
Charge Sharing and Keepers — the reliability edge cases above
Pull-Down Network Design — the series-vs-parallel PDN traps
NP / Zipper Domino — the answer to the non-inverting limitation
Clocking and Precharge Schemes — the timing edge cases