Exercises — Domino logic

Precharge ($\varphi =0$) and Evaluate ($\varphi =1$). Why: when $\varphi =0$ the precharge PMOS (gate driven by $\varphi$) is ON and pulls $X$ up; when $\varphi =1$ that PMOS is OFF and the bottom evaluate NMOS (also gated by $\varphi$) is ON, opening a possible discharge path.

$X=\text{HIGH }(1)$, and $Y=\overline{X}=\text{LOW }(0)$. Why: the PMOS charged $X$ to $V_{DD}$; the static inverter flips it, so the usable output $Y$ starts at 0. This "start-LOW" is the whole reason cascading is safe.

A static CMOS inverter on the dynamic node $X$. Domino = Dynamic + Inverter. Everything monotonic about domino follows from that inverter negating the naturally-falling node $X$.

Three NMOS in series (A, then B, then C) between node $X$ and the evaluate transistor. Why: the output is non-inverting, so the PDN must conduct exactly when $Y=1$, i.e. when $A\cdot B\cdot C=1$. Series NMOS conduct only when all gates are HIGH — that is logical AND. So a 3-input AND needs 3 series NMOS.

Two NMOS in parallel (A and B), both between $X$ and the evaluate transistor. Why: parallel NMOS conduct if any gate is HIGH = logical OR. $X$ discharges (so $Y$ rises to 1) when $A=1$ or $B=1$. This matches $Y=A+B$. See Pull-Down Network Design for the general series=AND / parallel=OR rule.

• Precharge ($\varphi =0$): PMOS on ⇒ $X=1$, $Y=0$.
• Evaluate ($\varphi =1$): the series NMOS are $A$(on)–$B$(off). Because $B$ is off the chain is broken, no discharge path. $X$ holds HIGH on $C_X$, so $Y$ stays $0$.
• Result $Y=0=1\cdot 0$. ✓ Correct.

Matches $A+B$ exactly.

Failure: after precharge, a plain dynamic output sits HIGH. At the instant evaluate begins, the downstream gate sees that HIGH on its PDN input before the upstream gate has decided to pull it LOW. A HIGH turns the downstream NMOS ON, discharging its dynamic node early. Since dynamic nodes are floating ($dQ/dt=0$), lost charge cannot be recovered — a permanent false evaluation (a race). Fix: a domino output starts LOW and is monotonically rising (can only go 0→1 during evaluate). So every downstream PDN input begins LOW ⇒ those transistors are OFF ⇒ no early discharge. A downstream node only discharges after an upstream output rises — the safe, ordered "falling dominoes" ripple.

Charge is conserved (isolated group of capacitors): $Q_{before}=C_X{V}_{DD}+C_a\cdot 0=40\text{ fF}\times 1.2\text{ V}=48\text{ fC}.$ After sharing, both caps sit at a common voltage on total cap $C_X+C_a$: $V_{final}=\frac{C_X{V}_{DD}}{C_X+C_a}=\frac{40\times 1.2}{40+10}=\frac{48}{50}=0.96\text{ V}.$ $\Delta V=V_{DD}-V_{final}=1.2-0.96=0.24\text{ V}.$ Meaning: $X$ sagged by 0.24 V (20% of $V_{DD}$). If the inverter's switching threshold sits below $0.96\text{ V}$ this particular case is safe, but bigger $C_a$ would sink it further — see the plot below.

Set $V_{final}=V_{th}$ and solve: $\frac{C_X{V}_{DD}}{C_X+C_a}=V_{th}\Rightarrow C_X+C_a=\frac{C_X{V}_{DD}}{V_{th}}\Rightarrow C_a=C_X\left(\frac{V_{DD}}{V_{th}}-1\right).$ With $V_{DD}/V_{th}=1.2/0.6=2$: $C_a=C_X(2-1)=C_X=40\text{ fF}.$ Physical meaning: when the internal node's capacitance equals $X$'s capacitance, the shared charge splits evenly and $X$ falls to exactly half of $V_{DD}$ — right at the threshold, the danger point where $Y$ may flip falsely. This is why we add a keeper.

The PDN must conduct when $(A+B)\cdot C=1$: that is $(A$ or $B)$ and $C$.

• Precharge PMOS: $V_{DD}\to X$, gate $=\varphi$.
• PDN top: NMOS $A$ and NMOS $B$ in parallel (the OR), between $X$ and an internal node $n$.
• PDN bottom: NMOS $C$ in series below that parallel pair, from $n$ to the evaluate NMOS.
• Evaluate NMOS: from bottom of PDN to ground, gate $=\varphi$.
• Static inverter: $X\to Y$.

Why this arrangement: series = AND, parallel = OR (from L2). $(A+B)$ is the parallel group; ANDing with $C$ means the whole group must sit in series with $C$. $X$ discharges only when the parallel group and $C$ conduct — exactly $(A+B)C$.

No. A domino output is non-inverting: it starts LOW and can only rise. An inverting function $\overline{A}$ would have to output HIGH when $A=0$ — but at evaluate start $Y$ is LOW, and if $A$ never rises there is no mechanism to drive $Y$ up to 1 through the normal PDN (the PDN pulls $X$ down = $Y$ up only when inputs are HIGH). So plain domino cannot invert. What to do: use dual-rail domino (compute both $Y$ and $\overline{Y}$ on complementary rails), or NP / Zipper Domino which alternates n- and p-type dynamic stages, or push the inversion into a static gate at the boundary. See the parent note's "big limitation."

• Type: a PMOS, connected $V_{DD}\to X$ (parallel to the precharge PMOS).
• Gate signal: $Y$ (the inverter output). When $X$ is HIGH, $Y=0$, so the keeper PMOS is ON and holds $X$ up. When $X$ falls, $Y$ rises to 1, turning the keeper OFF so it does not fight a legitimate discharge.
• Strength: weak (small W/L). It must be overpowered by the PDN during a true evaluation, only trickling charge otherwise.
• Protects: the case where $X$ should stay HIGH but is threatened by leakage or charge sharing (L3). The keeper refills the tiny lost charge so $V_X$ stays above the inverter threshold and $Y$ doesn't false-flip.

Conserved charge is unchanged (only $X$ started charged): $Q=C_X{V}_{DD}=40\times 1.2=48\text{ fC}.$ Total capacitance is now $C_X+C_a+C_b=40+10+6=56\text{ fF}$: $V_{final}=\frac{C_X{V}_{DD}}{C_X+C_a+C_b}=\frac{48}{56}=0.857\text{ V (3 s.f.)}.$ $\Delta V=1.2-0.857=0.343\text{ V}.$ Compared to L3.2 (single node, $V_{final}=0.96$, $\Delta V=0.24$): more exposed internal capacitance ⇒ deeper sag. The general rule: $V_{final}=C_X{V}_{DD}/(C_X+\sum C_i)$; every extra shared farad pulls $X$ lower. Deep, tall PDN stacks are the most charge-sharing-prone — a key argument for precharging internal nodes too (see Clocking and Precharge Schemes).

$V_{final}=\frac{C_X{V}_{DD}}{C_X+C_a}.$

• As $C_a\to \infty$: denominator $\to \infty$, so $V_{final}\to 0$. All of $X$'s charge is swallowed by the enormous empty node; $X$ collapses to ~0 V and $Y$ always false-flips to 1. Worst case.
• As $C_a\to 0$: $V_{final}\to C_X{V}_{DD}/C_X=V_{DD}$. A negligible internal cap steals essentially nothing; $X$ stays at $V_{DD}$. Safe — no keeper stress.

So the whole danger scales with the ratio $C_a/C_X$, exactly matching $\Delta V=V_{DD}{C}_a/(C_X+C_a)$. Design guidance: keep $C_X$ large relative to internal nodes.

Boolean → PDN. Conduct when $A\cdot (B+C)\cdot D=1$:

• $A$ (series) — top of chain from $X$.
• $(B$ parallel $C)$ — the OR group, in series below $A$.
• $D$ (series) — below the OR group, then to the evaluate NMOS.
• PDN NMOS count = 4 ($A,B,C,D$), plus 1 evaluate NMOS, plus 1 precharge PMOS, plus the 2 inverter transistors, plus a weak keeper PMOS.

Worst-case charge sharing. When $X$ discharges partially it can dump onto the internal node just below the first OFF transistor. If $A$ is ON but the $(B+C)$ group and $D$ decide the answer, the node between $A$ and the $(B+C)$ group (call it $n_1$) gets exposed and is deep in the stack (large parasitic cap from two series-connected transistor diffusions). That $n_1$, holding the most exposed capacitance, causes the biggest sag by L5.2's ratio rule.

Fix: add a small precharge PMOS on $n_1$ (gate $=\varphi$) so $n_1$ starts at $V_{DD}$ too — then when it connects to $X$ there's no empty capacitor to steal charge ($V_{final}=V_{DD}$ since both start high). Combine with the weak keeper on $X$ for leakage. This is the standard keeper + internal-precharge defense.

Two clock phases and their $\varphi$ ::: Precharge $\varphi =0$, Evaluate $\varphi =1$. Output level right after precharge ::: LOW (0). Property enabling cascading ::: Monotonically rising output (0→1 only). Charge-sharing final voltage of $X$ ::: $V_{final}=C_X{V}_{DD}/(C_X+\sum C_i)$. $C_a$ that drops $X$ to $V_{DD}/2$ ::: $C_a=C_X$. Keeper type, gate, strength ::: weak PMOS, gate $=Y$, $V_{DD}\to X$. Domino's fundamental limit ::: non-inverting only.