Domino logic — Hinglish notes

3.2.12 · Hardware › CMOS Circuit Design

Domino logic kyun exist karti hai?

Background: dynamic gate kaise kaam karta hai

Domino ka fix

YEH aapko kya deta hai — monotonicity. Levels trace karo:

Phase	Dynamic node $X$	Output $Y = \overline{X}$
Precharge ( $ϕ = 0$ )	HIGH ( $V_{D D}$ )	LOW (0)
Evaluate ( $ϕ = 1$ )	HIGH rehta hai ya 0 tak girta hai	LOW rehta hai ya 1 tak rise karta hai

Toh evaluation ke dauran, $Y$ LOW se start hota hai aur sirf rise (0→1) kar sakta hai — kabhi fall nahi karega. Isse monotonically rising signal kehte hain.

Ek banana kaise hai — worked construction

Goal: ek domino AND-gate Y = A·B banao.

PDN ke liye function chuno. Ek domino output $Y = \overline{X}$ hota hai, aur $X$ LOW jaata hai (toh $Y$ HIGH jaata hai) jab PDN conduct karta hai. Hum chahte hain $Y = A \cdot B$ , toh PDN ko tab conduct karna chahiye jab $A \cdot B = 1$ . Yeh step kyun? Dynamic node $X$ pe complement compute karta hai; inverter usse un-complement karta hai, toh PDN logic directly non-inverted output se match karti hai.
PDN = AND ke liye series NMOS. Do NMOS $A$ phir $B$ series mein $X$ aur evaluate transistor ke beech. Kyun? Series NMOS tabhi conduct karte hain jab dono on hon = logical AND.
Clocked precharge PMOS $V_{D D}$ se $X$ tak add karo, gate = $ϕ$ . Kyun? $X$ HIGH set karta hai ⇒ $Y$ LOW precharge ke dauran (required monotonic start).
Clocked evaluate NMOS neeche add karo, gate = $ϕ$ . Kyun? Precharge ke dauran koi bhi discharge block karta hai taaki $X$ cleanly charge ho sake.
Static inverter $X \to Y$ add karo. Kyun? Drive provide karta hai, levels restore karta hai, aur cascading ke liye monotonic non-inverting output produce karta hai.

Badi limitation

Recall Feynman: 12-saal ke bachche ko samjhao

Socho ek row of dominoes khade hain. Tum (clock) pehle sabko khada karte ho — woh hai precharge. Phir tum pehle wale ko girdate ho — evaluate. Har domino sirf gir sakta hai (upar se neeche), apne aap wapas khada kabhi nahi ho sakta. Kyunki woh sirf ek direction mein girte hain, ek ke baad ek, woh kabhi ek-doosre ko accident se nahi girate. Circuit mein, "khada rehna" = output LOW hai, "gir gaya" = output HIGH ho gaya, aur yeh one-way behavior gates ko safely aur quickly chain karne deta hai.

Flashcards

Plain dynamic gates directly cascade kyun nahi ho sakte?

Evaluate ke dauran unke outputs HIGH se start hote hain, toh ek downstream gate falsely discharge ho sakta hai upstream wale ke finish hone se pehle — ek non-monotonic race.

Kaun sa ek element ek dynamic gate ko domino gate mein badalta hai?

Dynamic output node pe ek static CMOS inverter.

Precharge ke baad domino output ki kya state hoti hai?

LOW (0), kyunki dynamic node HIGH hota hai aur inverter usse negate karta hai.

Kaunsi key property domino ko cascadable banati hai?

Evaluate ke dauran uska output monotonically rising hota hai (LOW se start, sirf 0→1 ja sakta hai).

Domino logic ki fundamental limitation kya hai?

Yeh sirf non-inverting hai — directly inverting function produce nahi kar sakta.

Ek floating dynamic node apni value kyun hold karta hai?

Koi conducting path nahi hone se dQ/dt=0, toh Q aur isliye V=Q/C constant rehta hai.

Charge sharing kya hai aur iska fix kya hai?

X se internal PDN node caps mein charge redistribute hone se V_X drop hota hai; weak keeper PMOS se fix hota hai.

Node X (cap C_X at Vdd) ka charge-sharing final voltage internal node (cap C_a at 0) ke saath?

V = C_X·Vdd/(C_X+C_a).

Domino AND gate Y=A·B ke liye PDN kaise arrange hota hai?

Do NMOS (A aur B) series mein, kyunki output non-inverting hota hai aur PDN A·B=1 ke liye conduct karta hai.

Keeper PMOS ka role kya hai?

Weak PMOS (gate=Y) jo X ko trickle-charge karta hai leakage/charge-sharing se ladne ke liye jab X ko HIGH rehna chahiye.

Connections

Dynamic CMOS Logic — woh precharge/evaluate base jis par domino build hoti hai
Static CMOS Logic — use hone wala inverter, aur inverting functions ke liye fallback
Charge Sharing and Keepers — reliability problem aur cure
Clocking and Precharge Schemes — $ϕ$ ki timing
NP / Zipper Domino — variants jo non-inverting limit ko overcome karte hain
Pull-Down Network Design — Boolean functions ko NMOS networks se map karna