3.2.11 · D5CMOS Circuit Design
Question bank — Dynamic CMOS logic
Before we start, a one-breath vocabulary refresh so no symbol is unearned:
True or false — justify
TRUE or FALSE: A dynamic gate needs both a PUN and a PDN, just like static CMOS.
False. The whole savings come from deleting the pull-up network and replacing it with one clocked precharge PMOS. Only an NMOS PDN remains, so the count is , not .
TRUE or FALSE: During the precharge phase, the input values are irrelevant to the output.
True. In precharge the foot NMOS is OFF, so the PDN is cut off from ground regardless of the inputs — the output is unconditionally pulled to . Inputs only matter during evaluate.
TRUE or FALSE: A dynamic gate can hold a logic 1 indefinitely, exactly like a static gate.
False. A static 1 is driven by a conducting PMOS; a dynamic 1 is only trapped charge on . Leakage bleeds it away, so the value is valid only for a finite hold time and must be refreshed each cycle.
TRUE or FALSE: A dynamic gate can hold a logic 0 indefinitely without leakage worries.
True (in the usual sense). A discharged output sits at ground through a conducting path (or near it); there is no trapped charge to leak away that would corrupt a 0. The fragile state is the trapped HIGH, not the LOW.
TRUE or FALSE: Series NMOS in the PDN gives you a dynamic NOR gate.
False. Series NMOS conduct only when all inputs are 1, giving = a NAND. Parallel NMOS (conducts if any input is 1) gives the NOR.
TRUE or FALSE: The precharge PMOS and the foot NMOS are never on at the same time.
True. Both are gated by : PMOS on when , foot NMOS on when . They are exact opposites, which is precisely what prevents a static -to-ground short.
TRUE or FALSE: For a 4-input gate, dynamic and static CMOS use the same number of transistors.
False. Dynamic uses ; static uses . The win grows with input count because static must build a wide, slow complementary network while dynamic reuses one precharge/foot pair.
TRUE or FALSE: Charge sharing can only pull the output down, never up.
True. Charge sharing spreads the precharged charge from the output onto a discharged internal node, so the shared voltage is always . It droops a HIGH; it can't manufacture extra charge to raise it.
Spot the error
Spot the error: "I removed the foot NMOS to save a transistor — the precharge PMOS being off in evaluate covers me."
The foot NMOS isn't there for the evaluate phase — it's there for precharge. Without it, if PDN inputs are high during precharge you get a direct ground short, wasting power and preventing a full precharge.
Spot the error: ", so a series-- PDN gives ."
Missing the inversion. Output is : when the path conducts the output discharges to 0. Series - therefore gives (NAND), not .
Spot the error: "I'll cascade two dynamic gates directly, output of gate 1 into an input of gate 2."
During precharge every dynamic output is HIGH. That HIGH can wrongly turn on gate 2's NMOS and discharge it before gate 1's real value settles — a monotonicity violation. Cascade via Domino logic (add a static inverter after each stage).
Spot the error: "A keeper is a strong PMOS that drives the output like a static pull-up."
A keeper is deliberately weak. It must be strong enough to replace leakage on a held HIGH, yet weak enough that the PDN can still yank the output LOW when it should. A strong keeper would fight the PDN and stall the discharge.
Spot the error: "Charge sharing is fixed by making smaller."
Backwards. The droop is — a smaller relative to makes the fraction smaller, so the output droops more. The real fixes are precharging internal nodes or adding a keeper.
Spot the error: "Dynamic logic is glitch-immune because the output only changes on clock edges."
The output value is decided during evaluate, but the trapped node is exposed to leakage, coupling, and charge sharing between edges. It is arguably more glitch-sensitive than static, not immune.
Why questions
Why does a dynamic gate use the same PDN topology as the equivalent static gate?
Because the PDN encodes exactly when to force the output to 0. Static and dynamic differ only in how the 1 is produced (complementary PUN vs. precharge), so the pull-down logic — hence the boolean function — is identical.
Why must inputs to a dynamic PDN only be allowed to go during evaluate, never ?
A discharge is irreversible mid-evaluate: once the trapped HIGH leaks to ground there's no pull-up to restore it. A input glitch that briefly opens a path would falsely and permanently discharge the node. Only monotonic inputs are safe.
Why is the precharge PMOS clocked instead of always-on?
An always-on PMOS would fight the PDN during evaluate (a constant -to-ground path plus a contested output), killing the speed and power advantage. Clocking it off during evaluate leaves the PDN a clean, uncontested discharge path.
Why does dynamic logic get faster than static as gates widen, especially for NOR?
A static NOR needs a series stack of PMOS (slow, because series PMOS have poor drive). Dynamic replaces that entire stack with one precharge PMOS, so the slow rising edge disappears — see Clocking and precharge timing.
Why can Domino logic cascade freely while raw dynamic logic cannot?
The added static inverter forces each stage's output LOW during precharge. A LOW input keeps the next NMOS off, so the only possible input transition during evaluate is a safe — exactly the monotonic rule raw dynamic logic violates.
Why does leakage threaten a stored 1 but not a strongly-driven 0?
Subthreshold and junction leakage slowly drain charge off the isolated ; nothing replenishes it, so a HIGH decays. A LOW is held at ground by a conducting path (or is simply the absence of charge), so there is no reservoir to leak.
Edge cases
Edge case: All PDN inputs are 0 throughout evaluate — what is the output and how is it held?
No conducting path exists, so the output stays at its precharged value = logic 1, held purely as trapped charge on (until leakage or the next precharge).
Edge case: The clock stalls in the evaluate phase () for a long time — what happens?
A held HIGH slowly leaks toward 0 (possible false 0), and an already-LOW output stays LOW. Without periodic precharge, dynamic logic loses its stored 1 — this is why the clock must keep running (or a keeper is added).
Edge case: In a series PDN, the internal node between two NMOS was left at 0 from a previous cycle, and now — is the output safe?
Logically it should stay HIGH (bottom transistor off, no path to ground), but turning on connects to the discharged internal . Charge shares to — a droop that can read as a false 0 if is comparable to .
Edge case: What if during charge sharing — is it still a problem?
Then , so the droop is negligible and the HIGH survives. Charge sharing only bites when internal capacitance is comparable to the output capacitance.
Edge case: Two inputs of a parallel (NOR-type) PDN both turn on during evaluate — any conflict?
No conflict; parallel branches to the same ground node simply provide two discharge paths, only speeding the discharge. Parallel means OR, and , which is the correct NOR output.
Edge case: A dynamic gate with zero fan-out load (nothing connected to the output) — does it still work?
The output still has its own drain and wiring capacitance as , so it precharges and evaluates normally — but the smaller makes it more vulnerable to leakage and charge sharing, since any parasitic is now relatively larger.
Recall One-line self-test
If you can state, without peeking, why a input glitch is fatal in evaluate but a is fine, you understand the single deepest trap on this page. Answer ::: A discharge is irreversible (no pull-up to undo it), so any input transition that could open a path — a glitch — risks permanently draining the trapped HIGH; a can only end in a decided state, never falsely trigger one.