Dynamic CMOS logic

3.2.11 · Hardware › CMOS Circuit Design

YEH HAI KYA

Gate ka structure:

1 PMOS (Mp) jo clock $ϕ$ se gate hota hai → precharge.
PDN of NMOS transistors implementing the logic function.
1 NMOS (Me, evaluation/foot transistor) jo $ϕ$ se gate hota hai → precharge ke dauran discharge rokta hai.

YEH KAAM KAISE KARTA HAI — do phases ko first principles se derive karo

Output node bas ek capacitor $C_{L}$ hai (agli stage ke gate caps + wire + drain caps). Uska voltage charge conservation follow karta hai: $Q = C_{L} V_{o u t}, I = C_{L} \frac{d V _{o u t}}{d t} .$

Precharge ( $ϕ = 0$ ):

$M p$ (PMOS) ka gate $= 0$ hai, toh $V_{GS} = 0 - V_{D D} = - V_{D D} < V_{tp}$ → ON. Yeh $V_{o u t} \to V_{D D}$ kheenchta hai.
$M e$ (foot NMOS) ka gate $= 0$ hai → OFF. Toh chahe PDN conduct karna chahe, ground tak koi path nahi — pull-up aur pull-down ke beech koi fight nahi (static CMOS ke ulat jo kabhi dono ko on nahi karta).

Evaluate ( $ϕ = 1$ ):

$M p$ off (gate $= V_{D D}$ ), $M e$ on (gate $= V_{D D}$ ).
Agar PDN inputs ek conducting path banaate hain, charge drain hota hai: $V_{o u t} : V_{D D} \to 0$ (logic 0).
Agar PDN conduct nahi kar raha, toh koi path nahi, isliye charge ruk jaata hai → $V_{o u t}$ $V_{D D}$ pe rehta hai (logic 1) — sirf trapped charge se hold hota hai.

Common Mistakes (Steel-manned)

Feynman

Recall 12-saal ke bacche ko explain karo

Imagine karo chhat pe ek paani ka tank (yeh output hai). Har raat aap use bharr dete ho (precharge). Din mein, drain ki taraf jaane wale darvaazon ki ek chain hoti hai (input switches). Agar saare sahi darvaaze khulein, paani khaali ho jaata hai (output = 0). Agar darvaaze band rahein, paani bhara rehta hai (output = 1). Chalaak trick yeh hai: aapko poora din pump chalane ki zaroorat nahi — bas ek baar bharr do aur tank ko paani rokke yaad karne do. Nuksan: paani dheere dheere leakta hai, aur agar tank ko khaali pipe se connect karein, level gir jaata hai (charge sharing). Isliye har cycle mein refill karna padta hai.

Flashcards

Dynamic CMOS gate ke do phases kya hain?

Precharge (

ϕ = 0

, output

V_{D D}

tak PMOS se charge) aur Evaluate (

ϕ = 1

, NMOS PDN se conditional discharge).

N-input dynamic gate ko static CMOS ke muqable mein kitne transistors chahiye?

Lagbhag

N + 2

(PDN + precharge PMOS + foot NMOS) vs static ke liye

2 N

Apne PDN ke given, dynamic gate kaunsa logic function realize karta hai?

f = \overline{PDN conducts}

; series NMOS → NAND-type, parallel NMOS → NOR-type.

Foot (evaluation) NMOS kyun zaroori hai?

Precharge ke dauran ground path tod deta hai taaki output fully charge ho sake aur static short-circuit path se bacha ja sake.

Dynamic logic apna output indefinitely kyun hold nahi kar sakta?

Logic 1 sirf

C_{L}

pe trapped charge hai; leakage use bleed kar deti hai, toh har cycle mein refresh karna padta hai (ya keeper use karo).

Charge sharing kya hai aur iska kya asar hota hai?

Jab output cap

C_{L}

ek discharged internal node

C_{X}

se connect ho; charge

V_{D D} C_{L} / (C_{L} + C_{X})

tak redistribute ho jaata hai, output droop karta hai → possible false 0.

Dynamic gates directly cascade kyun nahi ho sakte?

Precharge ke dauran outputs HIGH hote hain; dusre dynamic PDN ko woh feed karne se galat discharge ho sakta hai. Inputs evaluate ke dauran monotonic

0 \to 1

hone chahiye.

Domino logic kya hai aur yeh kya fix karta hai?

Har dynamic gate ke baad ek static inverter add kiya jaata hai taaki uska output precharge ke dauran LOW rahe aur sirf

0 \to 1

rise kare, safe cascading allow karta hai.

Dynamic logic mein sirf NMOS PDN kyun use hoti hai (PUN nahi)?

Pull-up ka kaam clocked precharge PMOS karta hai; PUN hatana hi transistor savings ka poora source hai.

Keeper transistor kya hota hai?

Ek weak PMOS jo output ko HIGH level hold karne ke liye feedback deta hai, leakage aur charge sharing ke against.

Connections

Static CMOS logic — $2 N$ -transistor baseline jise dynamic logic optimize karta hai.
Domino logic — cascading/monotonicity problem fix karta hai.
Charge sharing and keepers — reliability countermeasures.
MOS capacitance and $C_L$ — kyun charge storage aur leakage matter karti hai.
Clocking and precharge timing — woh $ϕ$ jo do phases alag karta hai.
Pull-down networks (series = AND, parallel = OR) — PDN synthesize kaise karein.

YEH HAI KYA

YEH KAAM KAISE KARTA HAI — do phases ko first principles se derive karo

Worked Examples

Common Mistakes (Steel-manned)

80/20 core

Feynman

Flashcards

Connections

Concept Map