Pull-up and pull-down networks — Hinglish notes

3.2.2 · Hardware › CMOS Circuit Design

Ek CMOS gate ek switch factory hai. Transistors ki do teams output node ke liye ladhti hain: ek team use HIGH kheenchti hai, doosri LOW — aur design ke hisaab se, dono kabhi ek saath nahi.

Core Idea

WHY PMOS pulls up, NMOS pulls down (first principles se)

HOW to build the networks: the duality rules

PUN aur PDN duals hain. Boolean function se ek banao, phir De Morgan se doosra lo.

Formula Deriving structure from the logic

Ek CMOS gate ek inverting function $Y = \overline{f (inputs)}$ compute karta hai.

Step 1 — PDN (output ko 0 pull karta hai jab $Y = 0$ , yaani jab $f = 1$ ):

Series NMOS ⇒ inputs ka AND (conduct karne ke liye dono ON hone chahiye).
Parallel NMOS ⇒ inputs ka OR (koi bhi ON ho to conduct hota hai).

Step 2 — PUN topological dual hai:

PDN mein series ⟷ PUN mein parallel
PDN mein parallel ⟷ PUN mein series
Har NMOS (input $A$ ) ek PMOS se map hota hai jisme same input $A$ hota hai (bubble/complement built-in hai kyunki PMOS low input se ON hota hai).

Yeh kyun kaam karta hai: De Morgan se, $\overline{A \cdot B} = \overset{ˉ}{A} + \overset{ˉ}{B}$ aur $\overline{A + B} = \overset{ˉ}{A} \cdot \overset{ˉ}{B}$ . Series↔AND aur parallel↔OR, isliye series/parallel swap karna hi De Morgan apply karna hai — automatically complementary conduction condition milti hai.

Maano $g_{P D N}$ = "PDN conducts" aur $g_{P U N}$ = "PUN conducts". Sahi design ke liye: $g_{P D N} = \overline{g_{P U N}} (complementary: never both, never neither)$ aur output hai $Y = \overline{g_{P D N}}$ (output tab high hota hai jab exactly PDN OFF ho aur PUN ON ho).

Worked Example 1 — the Inverter

Function: $Y = \overset{ˉ}{A}$ .

PDN: output LOW jaana chahiye jab $A = 1$ . Ek NMOS, gate $= A$ , $Y$ aur GND ke beech. Yeh step kyun? $f = A$ , isliye $A$ se control ek single series device.
PUN (dual): ek PMOS, gate $= A$ , $V_{D D}$ aur $Y$ ke beech. Kyun? Ek series device ka dual ek device hai; PMOS tab ON hota hai jab $A = 0$ , output high pull karta hai.
Check: $A = 0 \Rightarrow$ PMOS ON, NMOS OFF ⇒ $Y = 1$ . $A = 1 \Rightarrow$ NMOS ON ⇒ $Y = 0$ . ✔ Complementary.

Worked Example 2 — 2-input NAND

Function: $Y = \overline{A \cdot B}$ , isliye $f = A \cdot B$ .

PDN: output LOW sirf tab jab $A \cdot B = 1$ ⇒ dono ON hone chahiye ⇒ do NMOS series mein, gates $A$ aur $B$ . Kyun? AND ⇒ series.
PUN (dual): series→parallel ⇒ do PMOS parallel mein, gates $A$ , $B$ . Kyun? $\overline{A B} = \overset{ˉ}{A} + \overset{ˉ}{B}$ ⇒ output high agar koi bhi input low ho ⇒ parallel PMOS har ek pull up karta hai.
Check $A = B = 1$ : series NMOS conduct karta hai → $Y = 0$ ; dono PMOS off. Koi bhi doosra combination: kam se kam ek PMOS on → $Y = 1$ . ✔

Worked Example 3 — 2-input NOR

Function: $Y = \overline{A + B}$ , isliye $f = A + B$ .

PDN: LOW jab $A + B = 1$ ⇒ koi bhi ON pull low karta hai ⇒ do NMOS parallel mein. Kyun? OR ⇒ parallel.
PUN (dual): parallel→series ⇒ do PMOS series mein. Kyun? $\overline{A + B} = \overset{ˉ}{A} \overset{ˉ}{B}$ ⇒ output high sirf tab jab dono inputs low hon ⇒ series PMOS.
Check $A = B = 0$ : dono PMOS on (series) → $Y = 1$ ; dono NMOS off. Warna koi NMOS on → $Y = 0$ . ✔

Worked Example 4 — Compound gate (AOI)

Function: $Y = \overline{(A \cdot B) + C}$ .

PDN: $f = (A B) + C$ . $A B$ ⇒ series pair ( $A$ phir $B$ ); woh poori branch ek single NMOS $C$ ke parallel mein (woh OR hai).
PUN (dual): OR→series, AND→parallel: PMOS $C$ series mein (PMOS $A$ ∥ PMOS $B$ ) ke saath.
Ek single gate yeh kyun kar sakta hai: CMOS compound gates kisi bhi $\overline{AND-OR}$ (AOI) ya $\overline{OR-AND}$ (OAI) form ko ek single stage mein implement karte hain — NANDs ko chain karne se sasta aur fast.

Active Recall

PUN kis transistor type ka bana hota hai aur output ko kisse connect karta hai?

PMOS transistors se, output ko

V_{D D}

se connect karta hai.

PDN kis transistor type ka bana hota hai aur output ko kisse connect karta hai?

NMOS transistors se, output ko ground se connect karta hai.

Pull-up ke liye PMOS aur pull-down ke liye NMOS kyun use karte hain?

PMOS ek strong 1 pass karta hai, NMOS ek strong 0 pass karta hai; har ek ko wahan rakhna jahan woh best ho rail-to-rail output deta hai.

PDN mein series NMOS kaun sa Boolean operation implement karta hai?

AND (conduct karne ke liye dono ON hone chahiye).

PDN mein parallel NMOS kaun sa Boolean operation implement karta hai?

OR (koi bhi ek ON ho to conduct hota hai).

PUN topology PDN se kaise milti hai?

Yeh dual hai — series↔parallel swap karo, matching PMOS par same input rakho.

PUN/PDN ke liye golden design rule kya hai?

Har input ke liye, exactly ek network conduct karta hai:

g_{P D N} = \overline{g_{P U N}}

2-input NAND ke liye PDN aur PUN describe karo.

PDN: 2 NMOS series mein; PUN: 2 PMOS parallel mein.

2-input NOR ke liye PDN aur PUN describe karo.

PDN: 2 NMOS parallel mein; PUN: 2 PMOS series mein.

NMOS se degraded '1' kyun buri hoti hai?

Output

V_{D D} - V_{t n}

par cap ho jaata hai, noise margin cut ho jaata hai aur next stage mein static current leak ho sakti hai.

Static CMOS gate hamesha kaun sa logic form compute karta hai?

Ek inverting function

Y = \overline{f}

(AOI/OAI, inherently inverting).

Static CMOS mein static power kyun nahi hoti?

Complementary networks kabhi ek saath conduct nahi karte, isliye

V_{D D}

-to-GND ka koi continuous path nahi hota.

Connections

CMOS Inverter — sabse simple PUN/PDN pair.
NAND and NOR gates — series/parallel duality in action.
De Morgan's Theorem — duality rule ka mathematical basis.
Threshold Voltage and Body Effect — NMOS degraded 1 kyun deta hai.
Static vs Dynamic Power — complementary design power kyun bachata hai.
Pass Transistor Logic — kya hota hai jab tum strong/weak rule tod dete ho.