NMOS vs PMOS — Hardware notes

WHAT is each device?

The key structural fact: the source is defined by carrier flow, not by pin name.

In NMOS the source is the terminal at the lower potential (electrons enter from there).
In PMOS the source is the terminal at the higher potential (holes enter from there).

HOW does the gate voltage create a channel? (Derivation from scratch)

Start from the physical picture. The gate + oxide + substrate form a capacitor. The gate charge induces an opposite charge in the substrate.

NMOS on a p-substrate:

p-substrate is full of holes. Put $V_G$ positive relative to source.
Positive gate charge repels holes away from the surface → a depletion region.
Push $V_G$ higher: it now attracts minority electrons to the surface.
When the surface has as many electrons as the bulk had holes → strong inversion. The surface is now effectively n-type: a conducting n-channel bridges the two n regions.
The gate voltage at which this happens is the threshold $V_{Tn}$ .

So the condition to turn ON: $V_{GS} > V_{Tn} \quad (V_{Tn} > 0)$

Define the overdrive $V_{ov} = V_{GS} - V_{Tn}$ . Channel exists only when $V_{ov} > 0$ .

PMOS is the exact dual: everything's flipped in sign, so ON means $V_{GS} < V_{Tp} \quad\Longleftrightarrow\quad V_{SG} > |V_{Tp}|$

The one asymmetry that matters most

Electrons move faster than holes in silicon: $\mu_n \approx 2\text{–}3 \times \mu_p$

WHY? Holes conduct via the valence band which has heavier effective mass and more scattering. So for the same $W/L$ and overdrive, an NMOS delivers ~2–3× the current of a PMOS.

Consequence (the 80/20 takeaway): In CMOS, to make the pull-up (PMOS) as strong as the pull-down (NMOS), designers make the PMOS wider, typically $W_p \approx 2\text{–}3\,W_n$ . This single fact explains most CMOS layout asymmetry.

Worked examples

Common mistakes (Steel-man + fix)

Flashcards

What carriers conduct in an NMOS channel?

Electrons (n-channel).

What carriers conduct in a PMOS channel?

Holes (p-channel).

Turn-on condition for NMOS?

V_{GS} > V_{Tn}

, with

V_{Tn}>0

(gate driven HIGH).

Turn-on condition for PMOS?

V_{GS} < V_{Tp}

i.e.

V_{SG} > |V_{Tp}|

(gate driven LOW).

In PMOS, which terminal is the source?

The higher-potential terminal (where holes enter).

Why is PMOS made wider than NMOS in CMOS?

Because

\mu_p < \mu_n

; widening compensates lower hole mobility for equal drive.

Typical mobility ratio

\mu_n/\mu_p

About 2–3.

In a CMOS inverter, which device pulls the output HIGH?

The PMOS (pull-up).

Which device passes a strong logic 0?

NMOS.

Saturation current form for NMOS?

I_D=\tfrac12\mu_n C_{ox}\frac{W}{L}(V_{GS}-V_{Tn})^2

Define overdrive voltage.

V_{ov}=V_{GS}-V_{Tn}

(NMOS); channel exists only if

V_{ov}>0

What sizing gives equal NMOS/PMOS drive if

\mu_n=3\mu_p

W_p=3W_n

Recall Feynman: explain it to a 12-year-old

Imagine two kinds of water gate. The NMOS gate opens when you push its handle UP, and it lets fast little swimmers (electrons) through. The PMOS gate opens when you push its handle DOWN, and it lets slower bubbles (holes) through. Because the bubbles are slower, you make the bubble-gate a bit wider so the same amount gets through in the same time. In a computer we glue an up-gate and a down-gate together: when you push, one closes and the other opens — so the output always flips. That flip is how computers say "not."

Connections

MOSFET Structure & Threshold Voltage
CMOS Inverter
CMOS Logic Gates (Pull-up / Pull-down networks)
Carrier Mobility in Silicon
MOSFET Regions of Operation (Cutoff, Triode, Saturation)
Static & Dynamic Power in CMOS
BJT vs MOSFET

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, MOSFET basically ek voltage-controlled switch hai. Gate pe voltage lagao, aur wahi decide karta hai ki drain-source ke beech current chalega ya nahi. Do types hote hain: NMOS aur PMOS, aur ye ek dusre ke mirror-image hain. NMOS electrons se conduct karta hai aur ON hota hai jab gate HIGH ho ( $V_{GS} > V_{Tn}$ , threshold positive). PMOS holes se conduct karta hai aur ON hota hai jab gate LOW ho (gate source se neeche, threshold negative).

Ek important cheez: source hamesha carriers ke entry point se define hota hai, pin ke naam se nahi. NMOS me source low voltage wala terminal, PMOS me source high voltage wala terminal. Isliye PMOS me source ko $V_{DD}$ pe rakhte hain aur NMOS me source ko ground pe. Ye samajh gaye to CMOS inverter automatic clear ho jayega: input 0 diya to NMOS OFF, PMOS ON, output HIGH — yani NOT gate ban gaya, aur static current bhi nearly zero.

Sabse bada practical point: silicon me electrons holes se 2-3 guna fast chalte hain ( $\mu_n > \mu_p$ ). Iska matlab same size pe NMOS zyada strong hota hai. Isiliye designers PMOS ko chauda (wider) banate hain, roughly $W_p \approx 2$ se $3\,W_n$ , taaki pull-up aur pull-down dono barabar strong ho. Bas yehi ek asymmetry poore CMOS layout ka reason hai. Yaad rakho: "N goes UP, P goes DOWN" — NMOS pull-down, PMOS pull-up.