NMOS vs PMOS — Hinglish notes

2.4.10 · Hardware › Transistors: BJT & FET

HAR device KYA hai?

Key structural fact: source ko carrier flow se define kiya jaata hai, pin ke naam se nahi.

NMOS mein source woh terminal hota hai jo lower potential pe hota hai (electrons wahaan se enter karte hain).
PMOS mein source woh terminal hota hai jo higher potential pe hota hai (holes wahaan se enter karte hain).

Gate voltage channel KAISE banata hai? (Scratch se derivation)

Physical picture se shuru karo. Gate + oxide + substrate milke ek capacitor banaate hain. Gate charge substrate mein opposite charge induce karta hai.

NMOS ek p-substrate pe:

p-substrate holes se bhara hua hai. $V_{G}$ ko source ke relative positive karo.
Positive gate charge surface ke paas se holes ko repel karta hai → ek depletion region banta hai.
$V_{G}$ aur zyada badhao: ab yeh surface pe minority electrons ko attract karta hai.
Jab surface pe utne hi electrons ho jaate hain jitne bulk mein holes the → strong inversion. Surface ab effectively n-type hai: ek conducting n-channel dono n regions ko bridge karta hai.
Jis gate voltage pe aisa hota hai woh hai threshold $V_{T n}$ .

Toh ON hone ki condition hai: $V_{GS} > V_{T n} (V_{T n} > 0)$

Overdrive define karo $V_{o v} = V_{GS} - V_{T n}$ . Channel tabhi banta hai jab $V_{o v} > 0$ .

PMOS bilkul dual hai: sab kuch sign mein flip ho jaata hai, toh ON ka matlab hai $V_{GS} < V_{T p} ⟺ V_{S G} > ∣ V_{T p} ∣$

Woh ek asymmetry jo sabse zyada matter karti hai

Silicon mein electrons holes se zyada fast move karte hain: $μ_{n} \approx 2 - 3 \times μ_{p}$

Kyun? Holes valence band ke through conduct karte hain jisme effective mass zyada heavy hoti hai aur scattering bhi zyada hota hai. Toh same $W / L$ aur overdrive ke liye, ek NMOS ek PMOS se ~2–3× zyada current deliver karta hai.

Consequence (80/20 takeaway): CMOS mein, pull-up (PMOS) ko pull-down (NMOS) jitna strong banane ke liye, designers PMOS ko wider banate hain, typically $W_{p} \approx 2 - 3 W_{n}$ . Yahi ek fact CMOS layout asymmetry ka zyaadatar hissa explain karta hai.

Worked examples

Common mistakes (Steel-man + fix)

Flashcards

NMOS channel mein kaunse carriers conduct karte hain?

Electrons (n-channel).

PMOS channel mein kaunse carriers conduct karte hain?

Holes (p-channel).

NMOS ke liye turn-on condition?

V_{GS} > V_{T n}

, jisme

V_{T n} > 0

(gate HIGH driven).

PMOS ke liye turn-on condition?

V_{GS} < V_{T p}

yaani

V_{S G} > ∣ V_{T p} ∣

(gate LOW driven).

PMOS mein kaunsa terminal source hota hai?

Higher-potential terminal (jahaan holes enter karte hain).

CMOS mein PMOS ko NMOS se wider kyun banaya jaata hai?

Kyunki

μ_{p} < μ_{n}

; widening equal drive ke liye lower hole mobility ko compensate karta hai.

Typical mobility ratio

μ_{n} / μ_{p}

Lagbhag 2–3.

CMOS inverter mein kaunsa device output HIGH kheenchta hai?

PMOS (pull-up).

Strong logic 0 kaunsa device pass karta hai?

NMOS.

NMOS ke liye saturation current form?

I_{D} = \frac{1}{2} μ_{n} C_{o x} \frac{W}{L} (V_{GS} - V_{T n})^{2}

Overdrive voltage define karo.

V_{o v} = V_{GS} - V_{T n}

(NMOS); channel tabhi banta hai jab

V_{o v} > 0

Agar

μ_{n} = 3 μ_{p}

ho toh equal NMOS/PMOS drive ke liye kaunsi sizing chahiye?

W_{p} = 3 W_{n}

Recall Feynman: ek 12-saal ke bachche ko explain karo

Socho do tarah ke water gates hain. NMOS gate tab khulta hai jab tum iski handle UPAR push karte ho, aur yeh fast swimmers (electrons) ko andar jaane deta hai. PMOS gate tab khulta hai jab tum handle NEECHE push karte ho, aur yeh slower bubbles (holes) ko through jaane deta hai. Kyunki bubbles slower hain, tum bubble-gate ko thoda wider banao taaki same amount same time mein guzar sake. Computer mein hum ek up-gate aur ek down-gate ko saath chipkate hain: jab tum push karte ho, ek band hota hai aur doosra khul jaata hai — toh output hamesha flip hoti hai. Wahi flip hai jisse computers "not" kehte hain.

Connections

MOSFET Structure & Threshold Voltage
CMOS Inverter
CMOS Logic Gates (Pull-up / Pull-down networks)
Carrier Mobility in Silicon
MOSFET Regions of Operation (Cutoff, Triode, Saturation)
Static & Dynamic Power in CMOS
BJT vs MOSFET