A CMOS inverter is a voltage-controlled switch pair . As you sweep the input voltage from 0 to V D D V_{DD} V D D trade jobs . The VTC is simply the picture of V o u t V_{out} V o u t V i n V_{in} V in how sharp that hand-off is — a sharp transition means clean 0s and 1s that survive noise.
The Voltage Transfer Characteristic (VTC) is the plot of steady-state output voltage V o u t V_{out} V o u t V i n V_{in} V in
The defining physical constraint is Kirchhoff's Current Law
I D N = I D P I_{DN} = I_{DP} I D N = I D P
The NMOS drain current (pulling down ) must equal the PMOS drain current (pulling up ), because in steady state no net current charges the output node.
WHY equal currents? The output capacitor is done charging, so C d V / d t = 0 C\,dV/dt = 0 C d V / d t = 0 through both transistors in series from V D D V_{DD} V D D V o u t V_{out} V o u t
Define, for NMOS: V G S n = V i n V_{GSn}=V_{in} V GS n = V in V D S n = V o u t V_{DSn}=V_{out} V D S n = V o u t V T n > 0 V_{Tn}>0 V T n > 0 V S G p = V D D − V i n V_{SGp}=V_{DD}-V_{in} V S Gp = V D D − V in V S D p = V D D − V o u t V_{SDp}=V_{DD}-V_{out} V S D p = V D D − V o u t ∣ V T p ∣ |V_{Tp}| ∣ V T p ∣
Each transistor can be cutoff / saturation / triode :
Region
V i n V_{in} V in NMOS
PMOS
V o u t V_{out} V o u t
A
0 ≤ V i n < V T n 0\le V_{in}<V_{Tn} 0 ≤ V in < V T n cutoff
triode
≈ V D D \approx V_{DD} ≈ V D D
B
rising
saturation
triode
high, dropping
C
near V M V_M V M
saturation
saturation
steep drop
D
rising
triode
saturation
low, dropping
E
$V_{in}>V_{DD}-
V_{Tp}
$
triode
Region C is the near-vertical part. Both devices are in saturation acting like current sources, so a tiny change in V i n V_{in} V in huge change in V o u t V_{out} V o u t ≫ 1 \gg 1 ≫ 1
Why each step?
At V M V_M V M → because V i n = V o u t V_{in}=V_{out} V in = V o u t V D S n = V o u t > V i n − V T n = V G S n − V T n V_{DSn}=V_{out}>V_{in}-V_{Tn}=V_{GSn}-V_{Tn} V D S n = V o u t > V in − V T n = V GS n − V T n Set currents equal → KCL at output (defining constraint).Take square roots → both sides are perfect squares; taking \sqrt{} V M V_M V M β n ( V M − V T n ) = β p ( V D D − V M − ∣ V T p ∣ ) \sqrt{\beta_n}(V_M-V_{Tn})=\sqrt{\beta_p}(V_{DD}-V_M-|V_{Tp}|) β n ( V M − V T n ) = β p ( V D D − V M − ∣ V T p ∣ ) Divide by β n \sqrt{\beta_n} β n V M V_M V M → gives the boxed formula.
Symmetric inverter. Suppose V T n = ∣ V T p ∣ V_{Tn}=|V_{Tp}| V T n = ∣ V T p ∣ want V M = V D D / 2 V_M=V_{DD}/2 V M = V D D /2 r r r V M = V D D / 2 V_M=V_{DD}/2 V M = V D D /2 V T n = ∣ V T p ∣ = V T V_{Tn}=|V_{Tp}|=V_T V T n = ∣ V T p ∣ = V T V D D 2 = V T + r ( V D D − V T ) 1 + r ⇒ r = 1 \frac{V_{DD}}{2}=\frac{V_T+r(V_{DD}-V_T)}{1+r}\Rightarrow r=1 2 V D D = 1 + r V T + r ( V D D − V T ) ⇒ r = 1 Why this step? Plug V M = V D D / 2 V_M=V_{DD}/2 V M = V D D /2 r = 1 r=1 r = 1 β n = β p \beta_n=\beta_p β n = β p k n ′ ≈ 2 – 3 k p ′ k_n'\approx 2\text{–}3\,k_p' k n ′ ≈ 2 – 3 k p ′ W p ≈ 2 – 3 W n W_p\approx 2\text{–}3\,W_n W p ≈ 2 – 3 W n
Numerical V M V_M V M V D D = 1.8 V_{DD}=1.8 V D D = 1.8 V T n = 0.4 V_{Tn}=0.4 V T n = 0.4 ∣ V T p ∣ = 0.4 |V_{Tp}|=0.4 ∣ V T p ∣ = 0.4 r = β p / β n = 1.5 r=\sqrt{\beta_p/\beta_n}=1.5 r = β p / β n = 1.5 V M = 0.4 + 1.5 ( 1.8 − 0.4 ) 1 + 1.5 = 0.4 + 2.1 2.5 = 2.5 2.5 = 1.0 V V_M=\frac{0.4+1.5(1.8-0.4)}{1+1.5}=\frac{0.4+2.1}{2.5}=\frac{2.5}{2.5}=1.0\text{ V} V M = 1 + 1.5 0.4 + 1.5 ( 1.8 − 0.4 ) = 2.5 0.4 + 2.1 = 2.5 2.5 = 1.0 V Why this step? Larger r r r V M V_M V M upward toward V D D V_{DD} V D D V i n V_{in} V in V M = 1.0 > 0.9 V_M=1.0>0.9 V M = 1.0 > 0.9
The unity-gain points V I L V_{IL} V I L V I H V_{IH} V I H d V o u t d V i n = − 1 \dfrac{dV_{out}}{dV_{in}}=-1 d V in d V o u t = − 1
V O H ≈ V D D V_{OH}\approx V_{DD} V O H ≈ V D D V O L ≈ 0 V_{OL}\approx 0 V O L ≈ 0 Noise margins: N M H = V O H − V I H NM_H=V_{OH}-V_{IH} N M H = V O H − V I H N M L = V I L − V O L NM_L=V_{IL}-V_{OL} N M L = V I L − V O L
WHY unity-gain? For ∣ slope ∣ > 1 |\text{slope}|>1 ∣ slope ∣ > 1 attenuates noise (output swing smaller than input wiggle → signal restored). The − 1 -1 − 1
"V M V_M V M V D D / 2 V_{DD}/2 V D D /2
Why it feels right: textbooks draw the symmetric inverter, and 0/1 "should" be symmetric.
The truth: V M = V D D / 2 V_M=V_{DD}/2 V M = V D D /2 only when β n = β p \beta_n=\beta_p β n = β p V T n = ∣ V T p ∣ V_{Tn}=|V_{Tp}| V T n = ∣ V T p ∣ W W W r < 1 r<1 r < 1 V M < V D D / 2 V_M<V_{DD}/2 V M < V D D /2
"In region C the output is undefined/floating."
Why it feels right: the curve is nearly vertical, seems unstable.
The fix: it's perfectly defined — both transistors are saturated current sources and current balance pins V o u t V_{out} V o u t very sensitive (high gain), not floating. This region also draws a short-circuit current spike (both devices ON) — a real power cost.
"Sign of the slope doesn't matter for noise margin."
Why it feels right: people write "gain > 1".
The fix: an inverter's gain is negative ; the noise-margin condition is d V o u t d V i n = − 1 \frac{dV_{out}}{dV_{in}}=-1 d V in d V o u t = − 1 magnitude 1. Using + 1 +1 + 1
Recall Test yourself (hidden)
What constraint defines every point on the VTC? ⇒ I D N = I D P I_{DN}=I_{DP} I D N = I D P
In which region are BOTH transistors saturated? ⇒ the transition region (C), at/near V M V_M V M
What makes V M V_M V M V D D V_{DD} V D D r = β p / β n r=\sqrt{\beta_p/\beta_n} r = β p / β n
Define V I L , V I H V_{IL},V_{IH} V I L , V I H = − 1 =-1 = − 1
Recall Feynman: explain to a 12-year-oldImagine a see-saw with a "0-kid" on one end and a "1-kid" on the other, both pushing the output. You slide a lever (the input) from left to right. At first the 1-kid totally wins and the output is stuck HIGH. As you slide, the 0-kid gets stronger, and at one special spot they're exactly tied — the tiniest nudge tips the output all the way from HIGH to LOW super fast. That fast tipping is why computers can tell a clean "1" from a clean "0" even when the wire is a bit noisy. Making the two kids equally strong puts the tipping point right in the middle — the fairest, safest place.
"CS-SS-ST-SS-CS reads the same backwards" — the region sequence of (NMOS state, PMOS state) as V i n V_{in} V in C utoff→S at→S at(both)→T riode→cut for NMOS mirrors PMOS. Middle = S aturation S aturation = steep switching.
And: "Weaker P → V_M lower; boost W_p to center."
What DC constraint holds at every point of the CMOS inverter VTC? I D N = I D P I_{DN}=I_{DP} I D N = I D P (KCL: series transistors, output cap fully charged).
Which two device states occur simultaneously at V M V_M V M Both NMOS and PMOS in saturation.
Formula for switching threshold V M V_M V M r = β p / β n r=\sqrt{\beta_p/\beta_n} r = β p / β n V M = V T n + r ( V D D − ∣ V T p ∣ ) 1 + r V_M=\dfrac{V_{Tn}+r(V_{DD}-|V_{Tp}|)}{1+r} V M = 1 + r V T n + r ( V D D − ∣ V T p ∣ ) .
Condition on r r r V M = V D D / 2 V_M=V_{DD}/2 V M = V D D /2 V T V_T V T r = 1 r=1 r = 1 , i.e.
β n = β p \beta_n=\beta_p β n = β p .
Why must W p > W n W_p>W_n W p > W n V M V_M V M Hole mobility < electron mobility (
k p ′ < k n ′ k_p'<k_n' k p ′ < k n ′ ), so PMOS width must grow to equalize strength.
How are V I L V_{IL} V I L V I H V_{IH} V I H Points where
d V o u t / d V i n = − 1 dV_{out}/dV_{in}=-1 d V o u t / d V in = − 1 (unity-gain points).
Noise margins in terms of VTC levels? N M H = V O H − V I H NM_H=V_{OH}-V_{IH} N M H = V O H − V I H ,
N M L = V I L − V O L NM_L=V_{IL}-V_{OL} N M L = V I L − V O L .
What happens to V M V_M V M V M V_M V M increases (moves toward
V D D V_{DD} V D D ).
Why is the transition region so steep? Both devices act as saturated current sources; small
Δ V i n \Delta V_{in} Δ V in needs large
Δ V o u t \Delta V_{out} Δ V o u t to keep currents equal → high gain.
Extra cost of operating in the transition region? Short-circuit (crowbar) current, since both transistors conduct simultaneously.
CMOS Inverter — the device whose VTC this is.MOSFET IV Characteristics — triode/saturation square-law equations used in the derivation.Noise Margins — computed from V I L , V I H , V O H , V O L V_{IL},V_{IH},V_{OH},V_{OL} V I L , V I H , V O H , V O L Static CMOS Logic Gates — VTC generalizes to NAND/NOR via effective W/L.Short-circuit Power Dissipation — from the both-ON transition region.Propagation Delay — slope/gain relates to switching speed.
Ratio r = sqrt of beta_p/beta_n
Intuition Hinglish mein samjhoDekho, CMOS inverter basically do switch hain series mein — upar PMOS (pull-up) aur neeche NMOS (pull-down). Jab tum input voltage ko 0 se VDD tak slowly badhaate ho, to ye dono transistor apna "kaam" swap karte hain. VTC bas ek graph hai jo dikhata hai ki har input pe output kya hoga. Sabse important cheez: middle wala part bahut steep (khada) hota hai — matlab thoda sa input badalne se output pura HIGH se LOW ho jaata hai. Yehi sharpness digital logic ko clean 0 aur 1 deti hai, chahe wire pe thoda noise ho.
Har point pe ek hi rule chalta hai: NMOS ka current = PMOS ka current (KCL, kyunki output capacitor fully charged hai, koi extra current nahi bahta). Isi condition ko solve karke curve nikalta hai. Jaha input = output (45° line ko cross karti hai), us point ko V M V_M V M
Formula: V M = V T n + r ( V D D − ∣ V T p ∣ ) 1 + r V_M = \frac{V_{Tn}+r(V_{DD}-|V_{Tp}|)}{1+r} V M = 1 + r V T n + r ( V D D − ∣ V T p ∣ ) r = β p / β n r=\sqrt{\beta_p/\beta_n} r = β p / β n r r r V M V_M V M V M = V D D / 2 V_M=V_{DD}/2 V M = V D D /2 r = 1 r=1 r = 1 β n = β p \beta_n=\beta_p β n = β p W p > W n W_p > W_n W p > W n
