Voltage transfer characteristic (VTC): Exercises — Hardware deep dive

Before we start, one shared toolkit box you can refer back to.

Formula Toolkit (everything reused below)

KCL at the output — the one law behind every VTC point: $I_{D N} = I_{D P}$ . In steady state the output capacitor is fully charged, so the only current path is straight through the two series transistors; series means same current.
Saturation square-law (a transistor acting like a current source): $I_{D N} = \frac{1}{2} β_{n} (V_{in} - V_{T n})^{2}, I_{D P} = \frac{1}{2} β_{p} (V_{D D} - V_{in} - ∣ V_{T p} ∣)^{2}$ where $β = k^{'} \frac{W}{L}$ is the transistor's strength, $V_{T n}$ is the NMOS threshold (the input voltage you must exceed to turn it on), and $∣ V_{T p} ∣$ is the PMOS threshold magnitude.
Switching threshold — where the curve crosses the $4 5^{\circ}$ line ( $V_{in} = V_{o u t} = V_{M}$ ), with $r = β_{p} / β_{n}$ : $V_{M} = \frac{V _{T n} + r ( V _{D D} - ∣ V _{T p} ∣ )}{1 + r}$
Unity-gain points $V_{I L}, V_{I H}$ : where the slope $\frac{d V _{o u t}}{d V _{in}} = - 1$ .
Noise margins: $N M_{H} = V_{O H} - V_{I H}$ , $N M_{L} = V_{I L} - V_{O L}$ , with $V_{O H} \approx V_{D D}$ , $V_{O L} \approx 0$ .

See the parent for the derivations: Voltage transfer characteristic (VTC), MOSFET IV Characteristics, Noise Margins.

Level 1 — Recognition

L1.1 Read the constraint

Problem. At an arbitrary point on a CMOS inverter's VTC (not just $V_{M}$ ), which equation links the two transistor currents, and why?

Recall Solution

The link is == $I_{D N} = I_{D P}$ == (Kirchhoff's Current Law at the output node). Why: in DC steady state the output capacitor has finished charging, so $C d V / d t = 0$ — no current leaks into the node. The NMOS (pulling down) and PMOS (pulling up) sit in series between $V_{D D}$ and ground, and a series path carries one current. Equal currents is not special to $V_{M}$ ; it holds at every point on the curve.

L1.2 Name the region

Problem. Both transistors are in saturation simultaneously. Which of the five VTC regions is this, and what does the curve look like there?

Recall Solution

This is the transition region C, at/near $V_{M}$ . On the plot it is the near-vertical, steep drop in the middle. Both devices behave as current sources, so a tiny change in $V_{in}$ demands a huge change in $V_{o u t}$ to keep $I_{D N} = I_{D P}$ — that is the high-gain (slope $≫ 1$ in magnitude) part that cleans up logic levels.

Level 2 — Application

L2.1 Compute $V_{M}$

Problem. $V_{D D} = 1.2$ V, $V_{T n} = 0.35$ V, $∣ V_{T p} ∣ = 0.35$ V, and $r = β_{p} / β_{n} = 1$ . Find $V_{M}$ .

Recall Solution

What: plug into $V_{M} = \frac{V _{T n} + r ( V _{D D} - ∣ V _{T p} ∣ )}{1 + r}$ . Why $r = 1$ matters: equal strengths and equal thresholds is the symmetric case, so we expect the switching point dead-centre. $V_{M} = \frac{0.35 + 1 \cdot ( 1.2 - 0.35 )}{1 + 1} = \frac{0.35 + 0.85}{2} = \frac{1.2}{2} = 0.6 V$ Exactly $V_{D D} /2$ , confirming symmetry. ✔

L2.2 Effect of an asymmetric threshold

Problem. Keep $V_{D D} = 1.2$ V, $r = 1$ , $∣ V_{T p} ∣ = 0.35$ V, but raise the NMOS threshold to $V_{T n} = 0.5$ V. Does $V_{M}$ move up or down? Compute it.

Recall Solution

Predict first: a bigger $V_{T n}$ means the NMOS turns on later (needs more input voltage), so the pull-down is lazy — the output stays high longer — so $V_{M}$ should shift up. $V_{M} = \frac{0.5 + 1 \cdot ( 1.2 - 0.35 )}{2} = \frac{0.5 + 0.85}{2} = \frac{1.35}{2} = 0.675 V$ Indeed $0.675 > 0.6$ : it rose. ✔ (See Noise Margins — this now unbalances the margins.)

Level 3 — Analysis

L3.1 Design $r$ to hit a target $V_{M}$

Problem. $V_{D D} = 1.8$ V, $V_{T n} = ∣ V_{T p} ∣ = 0.4$ V. You want $V_{M} = 1.0$ V (shifted above centre for a noisy pull-down). What ratio $r = β_{p} / β_{n}$ achieves it?

Recall Solution

What: invert the $V_{M}$ formula for $r$ . Start from $V_{M} (1 + r) = V_{T n} + r (V_{D D} - ∣ V_{T p} ∣) .$ Collect the $r$ terms: $r [(V_{D D} - ∣ V_{T p} ∣) - V_{M}] = V_{M} - V_{T n}$ $r = \frac{V _{M} - V _{T n}}{( V _{D D} - ∣ V _{T p} ∣ ) - V _{M}} .$ Why this algebra: we know the outcome ( $V_{M}$ ) and want the cause ( $r$ ), so we solve the same equation the other way round. $r = \frac{1.0 - 0.4}{( 1.8 - 0.4 ) - 1.0} = \frac{0.6}{1.4 - 1.0} = \frac{0.6}{0.4} = 1.5.$ So $r = 1.5$ , meaning $β_{p} / β_{n} = r^{2} = 2.25$ : the PMOS must be 2.25× stronger than the NMOS. This matches the parent's worked example (that same $r = 1.5$ produced $V_{M} = 1.0$ V). ✔

L3.2 Convert $r$ into a width ratio

Problem. Continue L3.1. The process has $k_{n}^{'} = 3 k_{p}^{'}$ (electrons ~3× faster than holes) and equal channel lengths $L_{n} = L_{p}$ . What PMOS-to-NMOS width ratio $W_{p} / W_{n}$ gives $r = 1.5$ ?

Recall Solution

What: unpack $β = k^{'} \frac{W}{L}$ . With $L_{n} = L_{p}$ , $\frac{β _{p}}{β _{n}} = \frac{k _{p}^{'} W _{p}}{k _{n}^{'} W _{n}} = r^{2} = 2.25.$ Why: $r$ is set by silicon strength, and strength splits into the material factor $k^{'}$ and the geometry factor $W$ . We can only change geometry. Since $k_{n}^{'} = 3 k_{p}^{'} \Rightarrow k_{p}^{'} / k_{n}^{'} = 1/3$ : $\frac{1}{3} \cdot \frac{W _{p}}{W _{n}} = 2.25 \Rightarrow \frac{W _{p}}{W _{n}} = 6.75.$ The PMOS must be 6.75× wider than the NMOS. This is why real layouts have fat PMOS transistors — see CMOS Inverter and Static CMOS Logic Gates.

Figure — Voltage transfer characteristic (VTC)

Level 4 — Synthesis

L4.1 Gain and unity-gain points (why the slope is $- 1$ )

Problem. In region C both devices are saturated, and a first-order small-signal model gives the inverter's slope (gain) at $V_{M}$ as $A_{v} = \frac{d V _{o u t}}{d V _{in}} = - \frac{g _{mn} + g _{m p}}{g _{o n} + g _{o p}},$ where $g_{m}$ is a transconductance (how much drain current a transistor makes per volt of input) and $g_{o}$ is an output conductance (unwanted current leak per volt of output). Suppose $g_{mn} + g_{m p} = 0.9$ mS and $g_{o n} + g_{o p} = 0.05$ mS. (a) Find the gain. (b) In one sentence, why does its being far below $- 1$ guarantee good noise margins?

Recall Solution

(a) $A_{v} = - \frac{0.9 mS}{0.05 mS} = - 18.$ (b) The unity-gain points $V_{I L}, V_{I H}$ are where the slope equals $- 1$ ; if the peak slope is a steep $- 18$ , the curve crosses $- 1$ very close to $V_{M}$ on both sides. That squeezes the whole transition into a narrow input band, leaving wide flat plateaus at $V_{O H} \approx V_{D D}$ and $V_{O L} \approx 0$ — i.e. large $N M_{H} = V_{O H} - V_{I H}$ and $N M_{L} = V_{I L} - V_{O L}$ . High gain ⇒ fat noise margins.

L4.2 Full noise-margin budget

Problem. From a measured VTC: $V_{O H} = 1.8$ V, $V_{O L} = 0.0$ V, $V_{I H} = 1.05$ V, $V_{I L} = 0.75$ V. Compute $N M_{H}$ and $N M_{L}$ . Is the inverter symmetric?

Recall Solution

What: apply the definitions directly. $N M_{H} = V_{O H} - V_{I H} = 1.8 - 1.05 = 0.75 V$ $N M_{L} = V_{I L} - V_{O L} = 0.75 - 0.0 = 0.75 V$ Why symmetric: $N M_{H} = N M_{L} = 0.75$ V, so a noise spike of the same size is tolerated whether the wire sits HIGH or LOW. Balanced margins ⇒ $V_{M}$ near centre, exactly what an $r = 1$ design targets. See Noise Margins.

Level 5 — Mastery

L5.1 End-to-end inverter design

Problem. Design a CMOS inverter for a $1.0$ V supply that (i) switches at $V_{M} = 0.5$ V and (ii) is built on a process with $V_{T n} = ∣ V_{T p} ∣ = 0.3$ V, $k_{n}^{'} = 4 k_{p}^{'}$ , $L_{n} = L_{p}$ . Find (a) the required $r$ , (b) $β_{p} / β_{n}$ , (c) $W_{p} / W_{n}$ . Then (d) explain in physical terms what happens to short-circuit power and switching threshold if a manufacturing error makes the PMOS half as wide as designed.

Recall Solution

(a) Required $r$ . Using $r = \frac{V _{M} - V _{T n}}{( V _{D D} - ∣ V _{T p} ∣ ) - V _{M}}$ : $r = \frac{0.5 - 0.3}{( 1.0 - 0.3 ) - 0.5} = \frac{0.2}{0.7 - 0.5} = \frac{0.2}{0.2} = 1.$ (Sanity: symmetric thresholds + centred $V_{M}$ ⇒ $r = 1$ , exactly as theory predicts.) (b) Beta ratio. $β_{p} / β_{n} = r^{2} = 1^{2} = 1$ . (c) Width ratio. With $\frac{β _{p}}{β _{n}} = \frac{k _{p}^{'}}{k _{n}^{'}} \frac{W _{p}}{W _{n}} = 1$ and $k_{p}^{'} / k_{n}^{'} = 1/4$ : $\frac{1}{4} \cdot \frac{W _{p}}{W _{n}} = 1 \Rightarrow \frac{W _{p}}{W _{n}} = 4.$ (d) Half-width PMOS fault. Halving $W_{p}$ halves $β_{p}$ , so $r_{new} = \frac{1}{2} β_{p} / β_{n} = 0.5 \approx 0.707.$ New switching threshold: $V_{M} = \frac{0.3 + 0.707 ( 1.0 - 0.3 )}{1 + 0.707} = \frac{0.3 + 0.495}{1.707} = \frac{0.795}{1.707} \approx 0.466 V .$ $V_{M}$ drops (weaker pull-up loses the tug-of-war sooner), unbalancing the noise margins — $N M_{H}$ shrinks. Short-circuit current: the crowbar spike happens whenever both devices conduct during a switch; a weaker PMOS narrows and lowers that current's peak slightly, but the transition window shifts and can widen, so total short-circuit power per switch is not simply "halved" — it depends on the new overlap. See Short-circuit Power Dissipation and Propagation Delay (a weaker PMOS also slows the low-to-high output transition). ✔

Active recall

Recall Rapid checks

Constraint at every VTC point? ⇒ $I_{D N} = I_{D P}$ .
Given $V_{M}$ , solve for $r$ ? ⇒ $r = \frac{V _{M} - V _{T n}}{( V _{D D} - ∣ V _{T p} ∣ ) - V _{M}}$ .
$r = 1.5 \Rightarrow β_{p} / β_{n} = ?$ ⇒ $r^{2} = 2.25$ .
Unity-gain slope value? ⇒ $- 1$ (negative!).
Weaker PMOS moves $V_{M}$ which way? ⇒ down (toward $0$ ).

Connections

Voltage transfer characteristic (VTC) — the parent this drills.
CMOS Inverter — the device under design.
MOSFET IV Characteristics — the square-law used throughout.
Noise Margins — L4/L5 outcomes.
Short-circuit Power Dissipation, Propagation Delay — L5 consequences.