Voltage transfer characteristic (VTC): Visual walkthrough

We will build toward this and only this:

$V_{M} = \frac{V _{T n} + r ( V _{D D} - ∣ V _{T p} ∣ )}{1 + r}, r = β_{p} / β_{n}$

Nine steps. Each step tells you WHAT we just did, WHY we did it, and WHAT IT LOOKS LIKE.

Step 1 — The circuit: two switches fighting over one wire

WHAT. A CMOS Inverter is just two transistors stacked between a top rail and the ground. The top rail sits at a fixed voltage we call $V_{D D}$ ("the supply", e.g. $1.8$ volts). The bottom is $0$ volts (ground, "GND"). The wire between the two transistors is the output, at voltage $V_{o u t}$ . The input voltage $V_{in}$ is fed to both transistor "gates" (their control knobs) at once.

WHY. Before any algebra we must name every wire, because every symbol in the final formula is a voltage measured on one of these wires. No naming → no formula.

PICTURE. The top transistor (call it PMOS, orange) pulls the output up toward $V_{D D}$ . The bottom transistor (NMOS, blue) pulls the output down toward $0$ . They are wired in series — head to tail — so the same current $I$ flows through both.

Figure — Voltage transfer characteristic (VTC)

Step 2 — The one law that pins every point: same current

WHAT. In steady state (nothing changing, no load current leaking away), the current flowing down through the NMOS must exactly equal the current flowing down through the PMOS. We write:

$current in NMOS I_{D N} = current in PMOS I_{D P}$

WHY. The output wire has a tiny capacitance (think of it as a bucket that stores charge). When the voltage stops changing, the bucket is full and no current goes into it. So whatever current arrives from the top must leave through the bottom — there is nowhere else to go. This is Kirchhoff's Current Law: current in = current out at the node. This single equation is the engine of the whole derivation.

PICTURE. One current $I$ enters the output node from the PMOS and the same $I$ leaves through the NMOS. The bucket (capacitor) is drawn full, its arrow-in reading $0$ .

Step 3 — What "current in a MOSFET" even means (from zero)

WHAT. A MOSFET is a valve. Its gate voltage decides how far the valve opens; its drain–source voltage decides how hard the fluid is pushed. Two numbers matter for the NMOS:

$V_{GS n} = V_{in}$ — gate-to-source voltage = how far open the valve is.
$V_{D S n} = V_{o u t}$ — drain-to-source voltage = the pressure across it.

There is a minimum knob-turn before any current flows, called the threshold $V_{T n}$ (a small positive number, e.g. $0.4 V$ ). Below it the valve is shut (cutoff).

WHY. We cannot set two currents equal until we know the formula for each current. That formula depends on which "mode" the valve is in. So first we must learn the three modes. (See MOSFET IV Characteristics for the full square-law story.)

PICTURE. Three regimes drawn as valve pictures:

Cutoff: $V_{GS n} < V_{T n}$ → shut, $I = 0$ .
Triode (a.k.a. linear): valve open and low pressure → acts like a resistor.
Saturation: valve open and high pressure → acts like a current source (current stops caring about pressure).

Step 4 — Locate $V_{M}$ : where input equals output

WHAT. We define the switching threshold $V_{M}$ as the special input where the output equals the input:

$V_{in} = V_{o u t} = V_{M}$

Geometrically, this is where the VTC curve crosses the diagonal $4 5^{\circ}$ line $V_{o u t} = V_{in}$ .

WHY. Why pick this point and not another? Because it is the "tipping point" — the balance point of the see-saw where neither the HIGH nor the LOW side has clearly won. It is the single number that tells you where the sharp hand-off happens, and it is the natural anchor for Noise Margins. Choosing $V_{in} = V_{o u t}$ also makes the algebra collapse, as we're about to see.

PICTURE. The blue VTC curve dropping from $V_{D D}$ to $0$ ; the gray diagonal $V_{o u t} = V_{in}$ ; the green dot where they cross is $(V_{M}, V_{M})$ .

Step 5 — At $V_{M}$ BOTH valves are in saturation

WHAT. We claim that at $V_{M}$ the NMOS is saturated and the PMOS is saturated. Check the NMOS inequality. Saturation needs: $V_{D S n} > V_{GS n} - V_{T n} .$ Substitute $V_{D S n} = V_{o u t} = V_{M}$ and $V_{GS n} = V_{in} = V_{M}$ : $V_{M} > V_{M} - V_{T n} ⟺ 0 > - V_{T n} ⟺ V_{T n} > 0. ✓$

WHY. We must confirm the mode before we are allowed to use the square-law current formula — using the wrong mode's equation is the #1 way to derive nonsense. The inequality is satisfied automatically because $V_{T n} > 0$ is always true. By the mirror-image argument (swap roles, measure from $V_{D D}$ ), the PMOS is saturated too.

PICTURE. Both valves drawn open with high pressure — both are current sources at $V_{M}$ . This is region C of the parent's 5-region table, the near-vertical part of the curve.

Step 6 — Write both saturation currents, term by term

WHAT. Plug $V_{M}$ into each square law.

NMOS (knob $= V_{in} = V_{M}$ , threshold $V_{T n}$ ): $I_{D N} = \frac{1}{2} NMOS strength β_{n} (knob V_{M} - threshold V_{T n})^{2}$

PMOS. Its knob is measured from the top rail: $V_{S Gp} = V_{D D} - V_{in} = V_{D D} - V_{M}$ , and its threshold magnitude is $∣ V_{T p} ∣$ . So its overdrive is $(V_{D D} - V_{M}) - ∣ V_{T p} ∣$ : $I_{D P} = \frac{1}{2} PMOS strength β_{p} (PMOS knob V_{D D} - V_{M} - threshold mag. ∣ V_{T p} ∣)^{2}$

WHY. These are the only two currents that exist (series circuit). Everything downstream is algebra on these two expressions. Note the symmetry: the PMOS formula is the NMOS formula "read from the top" — replace $V_{M} \to V_{D D} - V_{M}$ and $V_{T n} \to ∣ V_{T p} ∣$ .

PICTURE. Two parabolas: NMOS current rising in $V_{M}$ (blue), PMOS current falling in $V_{M}$ (orange). Where they cross is where the currents are equal — that crossing is $V_{M}$ .

Step 7 — Set equal and take the square root

WHAT. Impose the law from Step 2, $I_{D N} = I_{D P}$ : $\frac{1}{2} β_{n} (V_{M} - V_{T n})^{2} = \frac{1}{2} β_{p} (V_{D D} - V_{M} - ∣ V_{T p} ∣)^{2}$ Cancel the $\frac{1}{2}$ on both sides, then take the positive square root of each side: $β_{n} (V_{M} - V_{T n}) = β_{p} (V_{D D} - V_{M} - ∣ V_{T p} ∣)$

WHY take a square root? Because both sides are perfect squares. A square-root turns a quadratic in $V_{M}$ into a linear equation in $V_{M}$ — and a linear equation we can solve by hand in one line. We keep the positive root because at $V_{M}$ each overdrive is positive (both valves are genuinely ON): $V_{M} - V_{T n} > 0$ and $V_{D D} - V_{M} - ∣ V_{T p} ∣ > 0$ .

PICTURE. The "un-squaring" drawn as folding both parabolas down into two straight lines; their crossing point is unchanged but now sits at the meeting of two ramps.

Step 8 — Collect $V_{M}$ and box the result

WHAT. Divide both sides by $β_{n}$ and let $r = \frac{β _{p}}{β _{n}} = β_{p} / β_{n} (PMOS-to-NMOS strength ratio) .$ Then: $V_{M} - V_{T n} = r (V_{D D} - V_{M} - ∣ V_{T p} ∣)$ Gather every $V_{M}$ on the left: $V_{M} + r V_{M} = V_{T n} + r (V_{D D} - ∣ V_{T p} ∣) ⟹ V_{M} (1 + r) = V_{T n} + r (V_{D D} - ∣ V_{T p} ∣)$

$V_{M} = \frac{V _{T n} + r ( V _{D D} - ∣ V _{T p} ∣ )}{1 + r}$

Reading the box term by term:

$V_{T n}$ — where the NMOS starts pulling; drags $V_{M}$ toward this value.
$V_{D D} - ∣ V_{T p} ∣$ — where the PMOS stops pulling; drags $V_{M}$ toward this value.
$r$ — the tug-of-war weight. It is a weighted average: the bigger $r$ (stronger PMOS), the more $V_{M}$ leans toward the PMOS-favored high end.

WHY. This is the payoff. The single free design knob is $r$ (set by transistor widths). Everything else is fixed by the process.

PICTURE. $V_{M}$ as a slider on a beam between the two anchors $V_{T n}$ and $V_{D D} - ∣ V_{T p} ∣$ , with $r$ as the balance weight sliding it left or right.

Step 9 — Edge & degenerate cases (never leave a gap)

WHAT & WHY. A formula you cannot stress-test is a formula you don't trust. We check the extremes.

Symmetric case, $r = 1$ (equal strengths, $V_{T n} = ∣ V_{T p} ∣ = V_{T}$ ): $V_{M} = \frac{V _{T} + 1 \cdot ( V _{D D} - V _{T} )}{2} = \frac{V _{D D}}{2} .$ Perfect center → equal $N M_{H}$ and $N M_{L}$ . Because holes are slower than electrons ( $k_{p}^{'} < k_{n}^{'}$ ), reaching $r = 1$ needs $W_{p} > W_{n}$ (typically $2$ – $3 \times$ ).
Weak PMOS, $r \to 0$ (tiny/absent pull-up): $V_{M} \to \frac{V _{T n} + 0}{1 + 0} = V_{T n} .$ The NMOS wins immediately; the tip happens as soon as the NMOS switches on. $V_{M}$ slides all the way down to the NMOS anchor.
Overwhelming PMOS, $r \to \infty$ (divide top & bottom by $r$ ): $V_{M} \to \frac{V _{D D} - ∣ V _{T p} ∣}{1} = V_{D D} - ∣ V_{T p} ∣.$ The pull-up holds the output HIGH until the very last moment the PMOS can conduct. $V_{M}$ slides all the way up to the PMOS anchor.
Sanity of the input range. For any finite $r > 0$ , $V_{M}$ is a weighted average of $V_{T n}$ and $V_{D D} - ∣ V_{T p} ∣$ , so it always lands strictly between those two anchors — never below $V_{T n}$ , never above $V_{D D} - ∣ V_{T p} ∣$ . Physically reassuring: the tipping point is always inside the region where a switch can actually happen.

PICTURE. The slider from Step 8 shown at its three limits ( $r = 0$ left anchor, $r = 1$ center, $r \to \infty$ right anchor), proving $V_{M}$ can never escape the beam.

The one-picture summary

Everything above, compressed: the two current parabolas, their crossing pinned by $I_{D N} = I_{D P}$ , the resulting $V_{M}$ as a weighted average sliding between $V_{T n}$ and $V_{D D} - ∣ V_{T p} ∣$ under the control of $r$ , and the finished VTC with $V_{M}$ marked on the $4 5^{\circ}$ line.

Recall Feynman: the whole walkthrough in plain words

Two little valves share one pipe between the ceiling ( $V_{D D}$ ) and the floor ( $0$ ). Because they're on the same pipe, the water flowing through them must match — that's our one rule. We hunt for the special input where the output equals the input (the tipping point $V_{M}$ ). Right there, both valves happen to be wide-open-but-choked, meaning each is trying to force a fixed flow. We write each valve's flow as "half its strength times overdrive-squared," set the two flows equal, and — because both sides are perfect squares — we un-square them, turning a curvy equation into a straight one. Solving that straight line gives $V_{M}$ as a fair-share average between where the bottom valve wakes up ( $V_{T n}$ ) and where the top valve gives up ( $V_{D D} - ∣ V_{T p} ∣$ ), with a weight $r$ that says who's stronger. Crank up the top valve's strength and the tipping point drifts toward the ceiling; weaken it and it slumps toward the floor; make them equal and it lands dead center — the fairest place, with equal room for noise on both sides.

Connections

Voltage transfer characteristic (VTC) — the parent this walkthrough derives.
CMOS Inverter — the circuit of Step 1.
MOSFET IV Characteristics — the square-law and mode definitions of Steps 3–6.
Noise Margins — why the location of $V_{M}$ matters.
Short-circuit Power Dissipation — the cost of Step 5's both-ON region.
Static CMOS Logic Gates · Propagation Delay — where a well-centered $V_{M}$ pays off.