Noise margins (NMH, NML)

Chapter: CMOS Circuit Design · Subtopic: Robustness of digital logic levels

Core idea

WHY it exists: because "0" and "1" are not points, they are ranges of voltage. The gap between the sender's promise and the receiver's expectation is the margin.

WHAT it measures: worst-case tolerable noise, split into HIGH noise margin (NMH) and LOW noise margin (NML).

HOW we get it: from four voltage levels defined on the transfer characteristic (VTC): $V_{OH}, V_{OL}, V_{IH}, V_{IL}$ .

Deriving the margins from first principles

We chain driver → receiver. The driver outputs a valid level; the receiver must accept it even after noise is added.

Case HIGH (a 1 travels down the wire): The driver guarantees at least $V_{OH}$ . The receiver still calls it a 1 as long as its input stays above $V_{IH}$ . Noise can only drop the received voltage (worst case). Tolerable drop:

$\boxed{\;NM_H = V_{OH} - V_{IH}\;}$

Why this subtraction? $V_{OH}$ is the ceiling we start from, $V_{IH}$ is the floor the receiver needs. The distance between them is how far noise may pull the signal down before failure.

Case LOW (a 0 travels down the wire): The driver guarantees at most $V_{OL}$ . The receiver still calls it a 0 as long as its input stays below $V_{IL}$ . Noise can only raise it. Tolerable rise:

$\boxed{\;NM_L = V_{IL} - V_{OL}\;}$

Why this order? Now $V_{IL}$ is the ceiling (receiver limit) and $V_{OL}$ is the floor (driver start); noise pushes the low signal up toward the limit.

Worked example 1 — generic numbers

Given: $V_{OH}=4.6\text{ V},\ V_{IH}=3.5\text{ V},\ V_{IL}=1.0\text{ V},\ V_{OL}=0.4\text{ V}$ .

$NM_H = 4.6-3.5 = 1.1\text{ V}$ Why: start from the guaranteed high (4.6), subtract the minimum the receiver needs (3.5).

$NM_L = 1.0-0.4 = 0.6\text{ V}$ Why: the receiver tolerates up to 1.0 V as a 0; driver sits at 0.4 V, so 0.6 V of upward noise is allowed.

Robustness $=\min(1.1,0.6)=0.6$ V — the LOW side is weaker.

Worked example 2 — ideal CMOS inverter (matched)

Worked example

A symmetric CMOS inverter with $V_{DD}=1.8$ V and matched transistors ( $\beta_n=\beta_p$ ) has, for large gain, near-rail-to-rail output: $V_{OH}\approx V_{DD}=1.8$ V, $V_{OL}\approx 0$ V. For an idealised sharp VTC switching at $V_M=V_{DD}/2=0.9$ V, take $V_{IH}\approx V_{IL}\approx V_M=0.9$ V.

$NM_H = 1.8-0.9 = 0.9$ V Why this step? rail output minus switching threshold. $NM_L = 0.9-0 = 0.9$ V Why this step? threshold minus 0 rail.

Takeaway: CMOS's rail-to-rail swing ( $V_{OH}=V_{DD}$ , $V_{OL}=0$ ) and symmetric threshold give large, balanced margins ( $\approx V_{DD}/2$ ) — that is exactly why CMOS is the dominant logic family.

Worked example 3 — Forecast then Verify

Worked example

Forecast: If I make the PMOS weaker (skew the inverter), $V_M$ moves down (toward ground). Predict what happens to the margins before computing.

Guess: $V_M \downarrow \Rightarrow V_{IL},V_{IH}\downarrow$ . Then $NM_L=V_{IL}-V_{OL}$ shrinks (its ceiling drops) and $NM_H=V_{OH}-V_{IH}$ grows. So margins become unbalanced.

Verify with numbers: $V_{OH}=1.8, V_{OL}=0$ . Skewed thresholds $V_{IL}=0.5, V_{IH}=0.7$ . $NM_L = 0.5-0 = 0.5$ V (fell from 0.9). $NM_H = 1.8-0.7 = 1.1$ V (rose from 0.9). Confirmed: skew trades one margin for the other. Symmetric design maximises the minimum margin.

Common mistakes

Active recall

Recall Try before revealing

Give the two margin formulas from memory.
Why the slope = −1 points?
In which direction does noise threaten a HIGH signal?
Why is CMOS margin roughly $V_{DD}/2$ each?

Answers: 1) $NM_H=V_{OH}-V_{IH}$ , $NM_L=V_{IL}-V_{OL}$ . 2) Boundary between noise attenuation and amplification. 3) Downward (pulls toward $V_{IH}$ ). 4) Rail-to-rail swing + threshold at $V_{DD}/2$ .

Recall Feynman: explain to a 12-year-old

Imagine passing a note that says "HIGH" or "LOW". Your friend's ears are a bit fuzzy. If you SHOUT "HIGH" very loud (near the top), even if some noise makes it a bit quieter your friend still hears "HIGH". The extra loudness you have to spare before your friend gets confused is the noise margin. There's one cushion for shouting (HIGH) and one for whispering (LOW). A good chip keeps both cushions fat so random buzzing never flips a 1 into a 0.

Connections

CMOS Inverter VTC — where $V_{IL},V_{IH},V_{M}$ come from.
Static Gain and Regenerative Property — why $|A_v|>1$ near $V_M$ restores levels.
Fan-out and Loading — degrades $V_{OH}/V_{OL}$ , eroding margins.
Power Supply Scaling — lower $V_{DD}$ shrinks absolute margins.
Static Noise Margin (SRAM butterfly curve) — the same idea applied to bit-cells.

What is the noise margin?

The maximum input noise voltage a gate can tolerate while still producing a valid output level.

Formula for HIGH noise margin?

NM_H = V_{OH} - V_{IH}

Formula for LOW noise margin?

NM_L = V_{IL} - V_{OL}

How are

V_{IL}

and

V_{IH}

defined on the VTC?

The input voltages where

dV_{out}/dV_{in} = -1

(unity-gain points).

Why choose the slope = −1 points?

They separate the region where the gate attenuates noise from where it amplifies it.

In which direction does noise threaten a stored HIGH?

Downward — it pulls the level toward

V_{IH}

In which direction does noise threaten a stored LOW?

Upward — it pushes the level toward

V_{IL}

Overall robustness of a gate?

\min(NM_H, NM_L)

Approx margins of an ideal symmetric CMOS inverter?

About

V_{DD}/2

each (rail-to-rail swing, threshold at

V_{DD}/2

Why must both margins be positive?

A non-positive margin means valid logic levels overlap the forbidden region → gate can misread even without noise.

Effect of skewing the inverter threshold on margins?

One margin grows and the other shrinks; symmetric design maximises the minimum margin.

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, digital circuit me "0" aur "1" koi exact voltage nahi hota — woh ek range hota hai. Real chip me wire par noise aata hai (padosi wires ki coupling, supply drop, ringing). Noise margin ka matlab hai: kitna extra noise voltage gate jhel sakta hai bina galat value read kiye. Yeh ek safety cushion hai driver ke output aur next gate ke input requirement ke beech.

Do margins hote hain. HIGH side ke liye driver kam se kam $V_{OH}$ deta hai, aur receiver tab tak "1" maanta hai jab tak voltage $V_{IH}$ se upar hai. Noise HIGH signal ko neeche girata hai, isliye $NM_H = V_{OH}-V_{IH}$ . LOW side ke liye driver max $V_{OL}$ deta hai, receiver tab tak "0" maanta hai jab tak voltage $V_{IL}$ se neeche hai. Noise LOW ko upar uthata hai, isliye $NM_L = V_{IL}-V_{OL}$ . Order ulta mat karna warna answer negative aa jayega — margin hamesha positive hona chahiye.

$V_{IL}$ aur $V_{IH}$ kahan se aate hain? VTC curve par jahan slope $=-1$ hota hai. Uske andar gate noise ko chhota kar deta hai (attenuate), bahar noise bada ho jata hai (amplify). Isliye woh −1 points exact boundary hain valid region ki.

CMOS itna popular kyun hai? Kyunki iska output rail-to-rail hota hai — $V_{OH}\approx V_{DD}$ , $V_{OL}\approx 0$ — aur threshold beech me $V_{DD}/2$ par. Isse dono margins lagbhag $V_{DD}/2$ , aur balanced ho jate hain. Yaad rakho: robustness $=\min(NM_H,NM_L)$ , dono ko fat rakho tabhi chip noise me bhi reliable rahega.

Core idea

The four critical voltages

Deriving the margins from first principles

Worked example 1 — generic numbers

Worked example 2 — ideal CMOS inverter (matched)

Worked example 3 — Forecast then Verify

Common mistakes

Active recall

Connections

Concept Map

Hinglish (regional understanding)

Go deeper — visual, from zero

Test yourself — CMOS Circuit Design

Connections