Propagation delay and rise - fall times — Hardware notes

1. What are we measuring?

WHY two different points (50% vs 10/90%)?

Delay uses 50% because that is the logic decision point — where "1" becomes "0" for the next gate.
Rise/fall use 10–90% because signals asymptote slowly near the rails; the 0%→100% time would be infinite (exponential never truly reaches the rail), so we clip the ends.

Figure — Propagation delay and rise - fall times

2. Deriving delay from first principles

WHAT is happening: to make the output fall, the NMOS pulls charge off $C_L$ down to ground.

The governing equation (charge conservation on the output node): $C_L \frac{dV_{out}}{dt} = -\,i_{DN}(t)$

The whole game is: what model do we use for the discharge current $i_{DN}$ ? Two useful models:

Model A — RC (transistor as a resistor)

When the drain–source voltage is small the transistor behaves like a resistor $R_{eq}$ . Then it's just an RC discharge: $C_L\frac{dV}{dt} = -\frac{V}{R_{eq}} \;\Rightarrow\; V(t)=V_{DD}\,e^{-t/(R_{eq}C_L)}$

Derive $t_{pHL}$ — set $V=V_{DD}/2$ : $\frac{V_{DD}}{2}=V_{DD}e^{-t_{pHL}/(R_{eq}C_L)} \;\Rightarrow\; e^{-t_{pHL}/\tau}=\tfrac12$ $\boxed{t_{pHL}=R_{eq}C_L\ln 2 \approx 0.69\,R_{eq}C_L}$ Why $\ln 2$ ? Because we cross the half-way point, and $-\ln(1/2)=\ln 2$ .

Derive $t_f$ (10%→90%) for the same exponential: $t_f = \tau\ln\frac{0.9V_{DD}}{0.1V_{DD}} = R_{eq}C_L\ln 9 \approx 2.2\,R_{eq}C_L$ Why $\ln 9$ ? Time to go from $0.9V_{DD}$ down to $0.1V_{DD}$ is $\tau[\ln(V_{DD}/0.1V_{DD})-\ln(V_{DD}/0.9V_{DD})] = \tau\ln 9$ .

Model B — Saturation-current (constant-current) model

Early in the switch, $V_{DS}$ is large so the transistor is saturated and delivers a roughly constant current $I_{DSAT}$ . Then: $C_L\frac{dV}{dt}=-I_{DSAT}=\text{const} \;\Rightarrow\; V(t)=V_{DD}-\frac{I_{DSAT}}{C_L}t$ Time to drop by $V_{DD}/2$ : $\boxed{t_{pHL}=\frac{C_L\,V_{DD}/2}{I_{DSAT}}=\frac{C_L V_{DD}}{2 I_{DSAT}}}$

3. Why $R_{eq}$ ≈ (something / current)?

The equivalent resistance is an average of the true $V/I$ ratio over the swing. A standard estimate uses the current at the two ends of the transition. A common closed form: $R_{eq}\approx \frac{3}{4}\frac{V_{DD}}{I_{DSAT}}\Big(1-\tfrac{7}{9}\lambda V_{DD}\Big)$ The point you must remember: $R_{eq}$ scales as $1/(W/L)$ — double the width, halve the resistance, halve the delay (until you also double the load you drive).

4. Worked examples

5. Common mistakes (steel-manned)

6. Feynman + memory aids

Recall Explain to a 12-year-old

Imagine filling a bucket (the capacitor) with a hose (the transistor). A bigger bucket takes longer to fill; a fatter hose fills it faster. Propagation delay is "how long until the bucket is half full" — that's when your friend downstream decides the light turned on. Rise time is "how long from nearly-empty (10%) to nearly-full (90%)" — how sharp the pour looks. Never wait for exactly 100% full, because the last few drops trickle in forever.

7. Flashcards

Why does a gate have any delay at all?

A finite drive current must charge/discharge the output load capacitance

C_L

;

C\,dV/dt = i

takes nonzero time.

Definition of propagation delay

t_{pHL}

Time from input crossing 50%

V_{DD}

to output crossing 50% while output goes High→Low.

Why is delay measured at 50%?

It's the logic threshold where the next gate flips its decision.

Why are rise/fall measured at 10–90% not 0–100%?

The exponential output approaches the rail asymptotically, so 0–100% time is infinite; 10–90% clips the slow tails.

RC-model formula for

t_{pHL}

t_{pHL}=0.69\,R_{eq}C_L=R_{eq}C_L\ln2

Where does the

\ln 2

come from?

From setting

e^{-t/\tau}=1/2

at the 50% crossing.

RC-model formula for fall time?

t_f=2.2\,R_{eq}C_L=R_{eq}C_L\ln9

(10%→90%).

Constant-current model for

t_{pHL}

t_{pHL}=C_L V_{DD}/(2 I_{DSAT})

; only half the swing matters.

Fixed ratio

t_f/t_{pHL}

for a pure exponential?

\ln9/\ln2 \approx 3.17

How does

R_{eq}

scale with transistor width

W

R_{eq}\propto 1/W

; wider transistor = lower resistance = faster.

Why make PMOS ~2× the NMOS width in a matched inverter?

PMOS mobility ~½ of NMOS; doubling

W_p

equalizes

R_{eqp}=R_{eqn}

t_r=t_f

Overall gate delay from the two?

t_p=\tfrac12(t_{pHL}+t_{pLH})

Connections

CMOS Inverter DC Transfer Characteristic — where $V_{50\%}$ / switching threshold comes from.
Equivalent Resistance of MOSFET — origin of $R_{eq}$ .
Load Capacitance Estimation — computing $C_L$ (wire + fan-out).
Logical Effort and Fan-out-of-4 — optimal sizing/buffering.
Dynamic Power Dissipation — same $C_L V_{DD}$ charge, different consequence (energy).
Elmore Delay — extending RC delay to multi-node RC trees.

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, koi bhi logic gate instantly output nahi badalta. Har output node pe ek capacitance $C_L$ hoti hai (wires + aage wale gates ki input capacitance), aur transistor sirf ek limited current de paata hai. Capacitor ko limited current se charge/discharge karne me time lagta hai — bas yahi propagation delay aur rise/fall time hai. Simple funda: $C\,dV/dt = i$ , isliye bada capacitor ya kamzor transistor = zyada delay.

Propagation delay matlab input ke 50% cross karne se lekar output ke 50% cross karne tak ka time. 50% kyun? Kyunki wahi wo point hai jahan agla gate decide karta hai ki "1" hai ya "0". RC model me discharge exponential hota hai, aur half-way point pe pahunchne me $\ln 2 \approx 0.69$ , isliye $t_p = 0.69\,RC$ yaad rakho.

Rise/Fall time thoda alag cheez hai — ye ek hi output edge ka 10% se 90% tak jaane ka time hai, yaani edge kitna sharp hai. 0% se 100% kyun nahi lete? Kyunki exponential rail ko kabhi exactly touch nahi karta, tails me hamesha thoda charge trickle karta rehta hai — isliye 10–90% convention. Ye ninety(90) ke $\ln 9 \approx 2.2$ se aata hai, so $t_r = 2.2\,RC$ .

Exam ke liye 80/20: sirf yaad rakho $t_p \propto C_L / \text{drive}$ . Transistor wide karo (W badhao) to $R_{eq}$ gir jaata hai aur gate fast ho jaata hai. Aur PMOS ko NMOS se ~2x wide banate hain kyunki uski mobility aadhi hoti hai — tabhi rise aur fall time barabar aate hain. Bas "69 for half, 22 for the edge" ratta maar lo.

Propagation delay and rise - fall times

1. What are we measuring?

2. Deriving delay from first principles

Model A — RC (transistor as a resistor)

Model B — Saturation-current (constant-current) model

3. Why $R_{eq}$ ≈ (something / current)?

4. Worked examples

5. Common mistakes (steel-manned)

6. Feynman + memory aids

7. Flashcards

Connections

Concept Map

Hinglish (regional understanding)

Go deeper — visual, from zero

Test yourself — CMOS Circuit Design

Connections