Propagation delay and rise - fall times: Exercises

Level 1 — Recognition

L1.1

Which timing quantity is measured input-50% → output-50%, and which is measured 10%→90% on the output alone?

Recall Solution

Propagation delay ( $t_{p H L}$ , $t_{p L H}$ ) is the input-50% → output-50% lag — a causal delay between two nodes.
Rise/fall time ( $t_{r}$ , $t_{f}$ ) is the 10%→90% (or 90%→10%) span on the output edge alone — the steepness of one edge.

L1.2

State, from memory, the RC-model formulas for $t_{p H L}$ and $t_{f}$ , and say where the numbers $0.69$ and $2.2$ come from.

Recall Solution

$t_{p H L} = 0.69 R_{e q} C_{L} = R_{e q} C_{L} ln 2, t_{f} = 2.2 R_{e q} C_{L} = R_{e q} C_{L} ln 9$

$0.69 = ln 2$ — from crossing the half-way point $e^{- t / τ} = \frac{1}{2}$ .
$2.2 = ln 9$ — from spanning 10% → 90%: $ln (0.9/0.1) = ln 9$ .

Level 2 — Application

L2.1

An inverter has $R_{e q n} = 8 k Ω$ and $C_{L} = 20 fF$ . Find $τ$ , $t_{p H L}$ , and $t_{f}$ .

Recall Solution

$τ = R_{e q n} C_{L} = 8000 \times 20 \times 1 0^{- 15} = 1.6 \times 1 0^{- 10} = 160 ps$ .
$t_{p H L} = 0.69 τ = 0.69 \times 160 = 110.4 ps$ .
$t_{f} = 2.2 τ = 2.2 \times 160 = 352 ps$ .

L2.2

Using the constant-current model with $C_{L} = 15 fF$ , $V_{D D} = 1.0 V$ , $I_{D S A T} = 150 μ A$ , find $t_{p H L}$ .

Recall Solution

$t_{p H L} = \frac{C _{L} V _{D D}}{2 I _{D S A T}} = \frac{15 \times 1 0 ^{- 15} \times 1.0}{2 \times 150 \times 1 0 ^{- 6}} = \frac{1.5 \times 1 0 ^{- 14}}{3 \times 1 0 ^{- 4}} = 5.0 \times 1 0^{- 11} = 50 ps .$ Why halve the swing? Delay is measured only to $V_{D D} /2$ , so only half the charge $C_{L} V_{D D} /2$ needs removing.

L2.3

A PMOS pull-up has $R_{e q p} = 20 k Ω$ , load $C_{L} = 10 fF$ . Find $t_{p L H}$ and $t_{r}$ .

Recall Solution

$τ = R_{e q p} C_{L} = 20000 \times 1 0^{- 14} = 2.0 \times 1 0^{- 10} = 200 ps$ .
$t_{p L H} = 0.69 \times 200 = 138 ps$ .
$t_{r} = 2.2 \times 200 = 440 ps$ .

Level 3 — Analysis

L3.1

An inverter measures $t_{p H L} = 138 ps$ (RC model). Someone tells you $C_{L} = 10 fF$ . Work backwards to find $R_{e q n}$ .

Recall Solution

From $t_{p H L} = 0.69 R_{e q n} C_{L}$ : $R_{e q n} = \frac{t _{p H L}}{0.69 C _{L}} = \frac{138 \times 1 0 ^{- 12}}{0.69 \times 10 \times 1 0 ^{- 15}} = \frac{138 \times 1 0 ^{- 12}}{6.9 \times 1 0 ^{- 15}} = 2.0 \times 1 0^{4} = 20 k Ω.$

L3.2

Both models are applied to the same inverter: $C_{L} = 10 fF$ , $V_{D D} = 1.2 V$ . The RC model gives $R_{e q} = 12 k Ω$ . What $I_{D S A T}$ makes the constant-current model predict the same $t_{p H L}$ ?

Recall Solution

RC model: $t_{p H L} = 0.69 \times 12000 \times 1 0^{- 14} = 0.69 \times 1.2 \times 1 0^{- 10} = 8.28 \times 1 0^{- 11} = 82.8 ps$ .
Set equal to constant-current model $t_{p H L} = \frac{C _{L} V _{D D}}{2 I _{D S A T}}$ and solve for $I_{D S A T}$ : $I_{D S A T} = \frac{C _{L} V _{D D}}{2 t _{p H L}} = \frac{10 \times 1 0 ^{- 15} \times 1.2}{2 \times 82.8 \times 1 0 ^{- 12}} = \frac{1.2 \times 1 0 ^{- 14}}{1.656 \times 1 0 ^{- 10}} = 7.25 \times 1 0^{- 5} A \approx 72.5 μ A .$ Both models are just two lenses on the same discharge — look at the figure below to see how the straight-line constant-current path and the curved exponential path cross the 50% line at nearly the same instant.

Figure — Propagation delay and rise - fall times

L3.3

A wire is added, doubling $C_{L}$ from $10 fF$ to $20 fF$ . $R_{e q n} = 15 k Ω$ is unchanged. By how much does $t_{p H L}$ change (absolute picoseconds and percentage)?

Recall Solution

Before: $t_{p H L} = 0.69 \times 15000 \times 10 \times 1 0^{- 15} = 0.69 \times 1.5 \times 1 0^{- 10} = 103.5 ps$ .
After: load doubled → $t_{p H L}$ doubles = $207 ps$ .
Change $= 207 - 103.5 = 103.5 ps$ , a $+ 100%$ increase. Why exactly double? $t_{p H L} \propto C_{L}$ linearly; nothing else changed, so the ratio is exactly 2.

Level 4 — Synthesis

L4.1 — Matched inverter sizing

NMOS mobility is twice PMOS ( $μ_{n} = 2 μ_{p}$ ). A minimum NMOS gives $R_{e q n} = 13 k Ω$ at width $W_{n}$ . You want a symmetric inverter ( $t_{r} = t_{f}$ ) driving $C_{L} = 8 fF$ . (a) What $W_{p} / W_{n}$ ratio is needed? (b) With that ratio, what is $R_{e q p}$ ? (c) Find the symmetric delay $t_{p} = \frac{1}{2} (t_{p H L} + t_{p L H})$ .

Recall Solution

(a) $R_{e q} \propto 1/ (μ W)$ . To make $R_{e q p} = R_{e q n}$ despite $μ_{p} = \frac{1}{2} μ_{n}$ , we need $W_{p} = 2 W_{n}$ , i.e. ratio $= 2$ . (b) With $W_{p} = 2 W_{n}$ , the PMOS resistance matches: $R_{e q p} = R_{e q n} = 13 k Ω$ . (c) Both edges now have the same $τ = 13000 \times 8 \times 1 0^{- 15} = 1.04 \times 1 0^{- 10} = 104 ps$ . $t_{p H L} = t_{p L H} = 0.69 \times 104 = 71.76 ps$ , so $t_{p} = 71.76 ps$ (they're equal, so the average is the same value).

See Logical Effort and Fan-out-of-4 for why designers often accept $W_{p} < 2 W_{n}$ to save input capacitance.

L4.2 — Two-stage buffer beats one stage

A single small inverter ( $R_{e q} = 20 k Ω$ , self-cap ignored) must drive $C_{L} = 200 fF$ . (a) Its delay? (b) Now insert a stage: stage 1 has $R_{e q} = 20 k Ω$ and drives an intermediate node of $40 fF$ ; stage 2 is 5× wider so $R_{e q} = 4 k Ω$ and drives the full $200 fF$ . Total delay? (c) Which is faster?

Recall Solution

(a) One stage: $t = 0.69 \times 20000 \times 200 \times 1 0^{- 15} = 0.69 \times 4 \times 1 0^{- 9} = 2.76 ns = 2760 ps$ . (b) Stage 1: $0.69 \times 20000 \times 40 \times 1 0^{- 15} = 0.69 \times 8 \times 1 0^{- 10} = 552 ps$ . Stage 2: $0.69 \times 4000 \times 200 \times 1 0^{- 15} = 0.69 \times 8 \times 1 0^{- 10} = 552 ps$ . Total $= 552 + 552 = 1104 ps = 1.104 ns$ . (c) The two-stage buffer is faster: $1104 ps < 2760 ps$ — about $2.5 \times$ quicker, even though it has more gates. The strong second stage does the heavy lifting on the big load.

Level 5 — Mastery

L5.1 — Full design under a clock constraint

You design an inverter that must finish switching within a $t_{p} \leq 60 ps$ budget while driving $C_{L} = 12 fF$ at $V_{D D} = 1.2 V$ . (a) What is the largest allowable $R_{e q n}$ (assume symmetric, so use $t_{p} = 0.69 R_{e q} C_{L}$ )? (b) A minimum-width NMOS gives $R_{e q} = 30 k Ω$ . By what factor must you widen it? (c) Widening the transistor by that factor multiplies its input gate capacitance by the same factor; the previous stage then sees a bigger load. If the previous stage's own $R_{e q} = 10 k Ω$ and the widened gate presents $6 fF$ of input cap, what extra delay does the previous stage now incur just to drive this input?

Recall Solution

(a) $R_{e q} \leq \frac{t _{p}}{0.69 C _{L}} = \frac{60 \times 1 0 ^{- 12}}{0.69 \times 12 \times 1 0 ^{- 15}} = \frac{60 \times 1 0 ^{- 12}}{8.28 \times 1 0 ^{- 15}} = 7.246 \times 1 0^{3} \approx 7.25 k Ω.$ (b) Need $R_{e q}$ down from $30 k Ω$ to $7.25 k Ω$ . Since $R_{e q} \propto 1/ W$ , widen by factor $\frac{30}{7.25} \approx 4.14 \times$ . (c) Previous stage delay to drive the $6 fF$ input: $t = 0.69 \times 10000 \times 6 \times 1 0^{- 15} = 0.69 \times 6 \times 1 0^{- 11} = 4.14 \times 1 0^{- 11} = 41.4 ps .$ The lesson: you bought a fast final stage but sold speed upstream — the extra input cap slowed the driver. This tug-of-war (drive strength vs input load) is precisely what Logical Effort and Fan-out-of-4 optimises. See also Load Capacitance Estimation and Dynamic Power Dissipation (wider = faster but burns more switching power).

L5.2 — Distributed wire (Elmore) sanity check

A resistive wire is split into two segments $R_{1} = R_{2} = 5 k Ω$ with capacitors $C_{1} = C_{2} = 4 fF$ at each node (a simple RC ladder). Using the Elmore delay rule — each capacitor is multiplied by the total resistance on the path from the source to that capacitor — estimate the delay to the far node.

Recall Solution

Elmore delay $= \sum_{i} (resistance from source to node i) \times C_{i}$ :

Node 1: resistance to source $= R_{1} = 5 k Ω$ ; term $= R_{1} C_{1} = 5000 \times 4 \times 1 0^{- 15} = 2.0 \times 1 0^{- 11} = 20 ps$ .
Node 2: resistance to source $= R_{1} + R_{2} = 10 k Ω$ ; term $= (R_{1} + R_{2}) C_{2} = 10000 \times 4 \times 1 0^{- 15} = 4.0 \times 1 0^{- 11} = 40 ps$ .
Total $t_{E l m or e} = 20 + 40 = 60 ps$ . Notice the far capacitor is weighted by both resistances — resistance nearer the source penalises everything downstream. Deep dive: Elmore Delay.

Connections

↑ Parent: Propagation delay and rise/fall times
Equivalent Resistance of MOSFET · Load Capacitance Estimation · Logical Effort and Fan-out-of-4 · Dynamic Power Dissipation · Elmore Delay · CMOS Inverter DC Transfer Characteristic