Propagation delay and rise - fall times: Question bank

Definition Two symbols this page leans on — keep these in view

== $R_{e q}$ (equivalent resistance)== : the average value of "voltage-across ÷ current-through" the transistor over the whole output swing. We pretend the on-transistor is a plain resistor of this value so the discharge becomes a simple RC circuit. It scales as $R_{e q} \propto 1/ (W / L)$ — a wider transistor is a fatter hose, hence lower resistance. Full derivation lives in Equivalent Resistance of MOSFET.
== $I_{D S A T}$ (saturation drain current)== : the roughly constant current a MOSFET delivers early in a transition when its drain–source voltage is large (the device is saturated). Typical values sit in the tens-to-hundreds of $μ A$ per transistor for a small logic device. It is the "drive strength" that fills or empties $C_{L}$ .

Both feed the same core idea: $t_{p} \propto C_{L} / drive$ , where "drive" is $1/ R_{e q}$ or $I_{D S A T}$ .

Picture the two thresholds first

WHY a figure before the questions: almost every trap below is really a confusion about where on the curve we are measuring. Look at the two edges once, and the answers stop being memorized rules.

Figure — Propagation delay and rise - fall times

The blue curve is the exponential fall $V (t) = V_{D D} e^{- t / τ}$ with $τ = R_{e q} C_{L}$ . The green dashed line marks the $50%$ level (where $t_{p H L}$ is read — the logic decision point). The orange band marks $90%$ down to $10%$ (where $t_{f}$ is read — the edge shape). Notice the curve flattens toward the bottom rail: it approaches $0$ but never touches it — that is why $0%$ – $100%$ time is infinite and we clip to $10$ – $90%$ .

This second figure derives the famous ratio: reading $t_{p H L}$ off the $50%$ crossing gives $τ ln 2$ ; reading $t_{f}$ across the $90% \to 10%$ span gives $τ ln 9$ . The $τ = R_{e q} C_{L}$ cancels in the ratio, leaving $t_{f} / t_{p H L} = ln 9/ ln 2 \approx 3.17$ for every pure exponential, regardless of device.

The third figure is the slew trap: a slow input (red) keeps both NMOS and PMOS partly on at once (the shaded overlap where both gate-drives sit near threshold). During that overlap the pull-down current is stolen by the fighting pull-up, so the output reaches its $50%$ point later — real delay grows with input slope.

True or false — justify

Answer each with T/F and one sentence of why — never a bare verdict.

True or false: A logic gate switches its output instantly the moment the input crosses threshold.

False. The output node has capacitance

C_{L}

and the transistor supplies only finite current, so

C_{L} d V / d t = i

forces a nonzero charging time — the delay.

True or false: Doubling only the load capacitance

C_{L}

(transistor unchanged) doubles the propagation delay.

True. Both models give

t_{p} \propto C_{L}

(

0.69 R_{e q} C_{L}

C_{L} V_{D D} /2 I_{D S A T}

), and neither the equivalent resistance

R_{e q}

nor the saturation current

I_{D S A T}

depends on the load, so delay scales linearly with

C_{L}

True or false: For a pure RC (exponential) output, the fall time

t_{f}

is always exactly

3.17 \times

the delay

t_{p H L}

True.

t_{f} / t_{p H L} = ln 9/ ln 2 \approx 3.17

(see figure s02), a ratio fixed by the 10–90% vs 50% definitions — it cancels

R_{e q} C_{L}

entirely and is independent of the device.

True or false: Making both NMOS and PMOS wider always makes a chip faster.

False. Wider transistors lower your

R_{e q}

but raise your gate's own input capacitance, which becomes the load the previous stage must drive — you can slow the stage before you.

True or false: In a symmetric (matched) inverter with

t_{r} = t_{f}

, the NMOS and PMOS have equal widths.

False. Because

μ_{n} \approx 2 μ_{p}

, matching requires

W_{p} \approx 2 W_{n}

so that

R_{e q p} = R_{e q n}

; equal widths would leave the PMOS about twice as resistive.

True or false: Propagation delay depends on the input's own rise/fall speed.

True (in reality). The idealized formulas assume a step input, but a slow input keeps both transistors partly on longer (figure s03), so real delay grows with input slope — this is why slew propagates down a chain.

True or false: Rise time and propagation delay measure the same physical thing from different start points.

False. Delay is a causal lag between two nodes (input-50% → output-50%); rise/fall is the steepness of one edge (10%→90% of the output alone) — they answer different questions.

True or false: A larger equivalent resistance

R_{e q}

improves (reduces) delay.

False.

t_{p} \propto R_{e q}

, so larger

R_{e q}

(a weaker, narrower transistor) means slower switching;

R_{e q} \propto 1/ W

, so you want it small.

Spot the error

Each statement contains a flaw. Name it.

"Rise time is the time for the output to swing from 0% to 100% of

V_{D D}

The output approaches the rail asymptotically (exponentially, see figure s01), so it never truly reaches 0% or 100% — that time is infinite; the convention clips to 10%–90%.

"Since delay is

0.69 R_{e q} C_{L}

, I'll use the transistor's small-signal on-resistance at

V_{D S} = 0

for

R_{e q}

The equivalent resistance

R_{e q}

is an average of

V / I

over the whole swing (near-saturation at the start, triode at the end), not the tiny-

V_{D S}

triode resistance — that would badly underestimate delay.

"Delay is measured at 50% because the output is exactly halfway, which is easiest to see on a scope."

The real reason is logical, not visual:

V_{D D} /2

is the switching threshold of the next gate — the voltage at which it flips its decision.

t_{p H L} = C_{L} V_{D D} / (2 I_{D S A T})

uses

V_{D D} /2

because half the transistors are conducting."

The

V_{D D} /2

appears because delay is measured only to the halfway point, so only half the voltage swing's worth of charge must be moved — it has nothing to do with device count.

"Adding a buffer stage always increases total path delay because it adds a gate."

For a very large load, one small gate is crippled by

C_{L} / drive

; a chain of progressively sized buffers can drive the load faster overall — delay tracks

C_{L} / drive

, not gate count.

"To cut delay in half, just shrink the transistor width to lower its gate capacitance."

Shrinking

W

raises

R_{e q} \propto 1/ W

, which slows the pull-down of its own output — the reduced input cap only helps the previous stage.

"Since NMOS and PMOS in an inverter both drive the same

C_{L}

t_{p H L} = t_{p L H}

automatically."

Only if the resistances match; with equal widths the PMOS is ~2× more resistive, so

t_{p L H} > t_{p H L}

unless you size

W_{p} = 2 W_{n}

Why questions

Why does the factor

ln 2

(≈0.69) appear in the RC delay but

ln 9

(≈2.2) in the fall time?

Delay crosses one point (50%), giving

- ln (1/2) = ln 2

; fall time spans two points (90% down to 10%), giving

ln (0.9/0.1) = ln 9

— the log of the ratio of the two clip levels (figure s02).

Why do the RC model and the constant-current model give the same proportionality

t_{p} \propto C_{L} / drive

despite different physics?

Both come from

C_{L} d V / d t = - i

; whether

i

falls exponentially (resistor

R_{e q}

) or stays constant (saturation current

I_{D S A T}

), the time to move a fixed charge

C_{L} Δ V

still scales as charge over current.

Why does the PMOS being weaker mean the pull-up (rising) edge is naturally slower than the pull-down?

Weaker PMOS ⇒ larger

R_{e q p}

⇒ larger

t_{p L H} = 0.69 R_{e q p} C_{L}

, so the low→high transition lags the high→low unless the PMOS is widened.

Why is the overall gate delay defined as the average

t_{p} = \frac{1}{2} (t_{p H L} + t_{p L H})

rather than one of them?

A gate's output rises on some switches and falls on others; the average represents the typical delay a signal experiences regardless of edge direction.

Why does a slow (slowly-changing) input signal increase a gate's delay?

While the input lingers near threshold, both transistors conduct simultaneously (the shaded overlap in figure s03), the pull-up fights the pull-down and wastes current, delaying the moment the output reaches its own 50% point.

Why do we care about the slowest path's delay for maximum clock frequency, not the average?

The clock period must be long enough for every signal to settle before the next edge; the slowest (critical) path sets that limit, so it alone caps the frequency.

Why does doubling

W

not necessarily double the speed of a real gate driving the next identical gate?

Doubling

W

halves

R_{e q}

but also doubles the gate's own input capacitance, so the load presented to the previous stage doubles too — the net speedup is diluted (this is the fan-out-of-4 tradeoff).

Edge cases

What happens to

t_{f}

(10%→90% time) if

C_{L} \to 0

(no load)?

\to 0

: with nothing to charge, the exponential's time constant

R_{e q} C_{L} \to 0

, so the edge becomes ideally sharp (real parasitics keep it finite).

What is the theoretical 0%→100% transition time for a pure RC output?

Infinite — the exponential

V_{D D} e^{- t / τ}

approaches the rail but never equals it (figure s01), which is exactly why the 10–90% clip is used.

R_{e q n} = R_{e q p}

(perfectly matched inverter), what is the relation between

t_{p H L}

and

t_{p L H}

They are equal, so the average gate delay

t_{p}

equals each individually and the output edges are symmetric.

For a degenerate "infinitely strong" transistor (

R_{e q} \to 0

I_{D S A T} \to \infty

), what is the delay?

Zero — but this is unphysical; real transistors have finite

W / L

and current, so delay is always positive.

If the input is a perfect step but the output still takes time, where does that time come from?

Entirely from the RC charging of

C_{L}

through the transistor — the delay is an intrinsic property of the output node, not of the input's speed.

Which second-order effects can shift the real

R_{e q}

away from the ideal

\frac{3}{4} V_{D D} / I_{D S A T}

estimate?

Channel-length modulation (

λ

) makes

I_{D S A T}

creep up with

V_{D S}

, lowering

R_{e q}

; body effect raises the threshold

V_{T}

of a stacked transistor (its source is above ground), weakening it and raising

R_{e q}

; and $V_{T}$ shifts from temperature or process lower the drive and raise

R_{e q}

at hot/slow corners.

Why does a transistor stacked above another (its source not at ground) drive more weakly, raising the path's

R_{e q}

Body effect: with the source lifted above the body voltage, the effective threshold

V_{T}

rises, so

V_{GS} - V_{T}

(the overdrive) shrinks and the delivered current

I_{D S A T}

drops — the equivalent resistance climbs.

Recall

Recall The three "same word, different meaning" traps

50% vs 10–90%: delay uses 50% (logic threshold across two nodes); rise/fall use 10–90% (edge shape on one node).
$ln 2$ vs $ln 9$ : one crossing vs a span of two clip levels.
Wider $W$ : helps your output ( $R_{e q} ↓$ ) but hurts the stage feeding you (input cap $↑$ ).

Recall What

$R_{e q}$ and $I_{D S A T}$ actually mean $R_{e q}$ ::: the average $V / I$ of the on-transistor over the swing, letting us treat it as a plain resistor; $R_{e q} \propto 1/ (W / L)$ . $I_{D S A T}$ ::: the near-constant saturation current (tens–hundreds of $μ A$ ) the device delivers when $V_{D S}$ is large — the "drive strength".

Connections

Parent: Propagation delay and rise/fall times
Equivalent Resistance of MOSFET — where $R_{e q} \propto 1/ W$ and the second-order effects come from
Load Capacitance Estimation — what sets $C_{L}$
Logical Effort and Fan-out-of-4 — the width-vs-load tradeoff behind the sizing traps
CMOS Inverter DC Transfer Characteristic — the 50% switching threshold
Elmore Delay — delay of multi-node RC paths
Dynamic Power Dissipation — the other cost of charging $C_{L}$