Propagation delay and rise - fall times: Foundations

This page assumes you have seen none of the notation the parent note throws at you. We build each symbol from a picture, in an order where every new symbol only leans on ones already earned. Nothing here contradicts the parent — it is the missing floor beneath it. When you are ready, jump up to the parent topic.

0. Voltage, current, charge — the three that start everything

Before any transistor or capacitor, three plain physical words.

Why the topic needs these: the whole page is one sentence — "push charge onto/off a node with a current." $V$ , $i$ , $Q$ are the three nouns in that sentence.

The single relationship that ties current to charge is just the definition of "per second": $i = \frac{d Q}{d t}$

Read $\frac{d Q}{d t}$ out loud as "the rate at which charge $Q$ changes as time $t$ ticks forward." The little $d$ 's mean "a tiny change in." So $\frac{d Q}{d t}$ = "tiny change in charge ÷ tiny change in time" = flow rate = current. That's all a derivative is here: a rate. We need it because the topic is entirely about rates of charging.

1. The capacitor $C$ and the load capacitance $C_{L}$

Figure — Propagation delay and rise - fall times

Picture: a bucket. $V$ = how high the water sits, $Q$ = how much water is in it, $C$ = how wide the bucket is. A wide bucket ( $C$ big) holds lots of water even at a modest height.

Why the topic needs it: the output is this bucket. No bucket, no delay. Everything downstream is "how long to fill/empty $C_{L}$ ."

Now combine the two things we have. Start from $Q = C V$ and ask how the charge changes as the voltage changes on a fixed capacitor. Taking the rate of both sides: $i = \frac{d Q}{d t} = C \frac{d V}{d t}$

2. The supply $V_{D D}$ , ground, and the 50 % point

Picture: a vertical ruler from $0$ (bottom) to $V_{D D}$ (top). Mark $10%$ , $50%$ , $90%$ lines across it. Every timing number is measured against these horizontal lines.

Why the topic needs $50%$ specifically: logic is a decision, and the decision point sits in the middle. Crossing $V_{D D} /2$ is the moment "the answer changed."

3. The MOSFET as a switch, a resistor, and a current source

The transistor is the hose that fills or empties the bucket. The parent note models it three different ways depending on how careful you want to be.

Why two models? They answer the same question ("how fast does the bucket empty?") with different accuracy. The resistor model gives a clean exponential; the constant-current model gives a straight-line drop. The parent note uses both.

The two sub-transistors of an inverter get their own labels:

== $R_{e q n}$ / $I_{D S A T, n}$ == — the NMOS, which pulls the output down to ground (output goes High→Low).
== $R_{e q p}$ / $I_{D S A T, p}$ == — the PMOS, which pulls the output up to $V_{D D}$ (output goes Low→High).

Why the split matters: pull-down and pull-up are different transistors with different strengths, so the fall edge and rise edge take different times. That is exactly why the parent has both $t_{p H L}$ and $t_{p L H}$ .

4. The exponential $e^{- t / τ}$ and the time constant $τ$

This is the one piece of "scary maths" the parent leans on, so we earn it fully from zero.

Set-up (WHAT): a full bucket at height $V_{D D}$ drains through a resistor $R_{e q}$ . Plug Ohm's law $i = V / R_{e q}$ into the master equation $i = - C d V / d t$ (the minus sign because the bucket is emptying, so $V$ is falling): $C_{L} \frac{d V}{d t} = - \frac{V}{R _{e q}}$

WHY this shape: the drain current is proportional to the height still left ( $i = V / R$ ). So a full bucket empties fast, and as it empties it slows down — the flow chokes itself. Any quantity whose fall-rate is proportional to how much remains follows the exponential decay: $V (t) = V_{D D} e^{- t / τ}, τ = R_{e q} C_{L}$

WHAT the number $e$ is: $e \approx 2.718$ is just the special base for which "rate of change equals the current value." That's the only base that makes self-choking decay come out clean, which is why it shows up here and nowhere by choice.

Two fractions matter, and now you can read the parent's magic numbers straight off:

Cross to 50 % ( $f = \frac{1}{2}$ ): $t = τ ln 2 \approx 0.69 τ$ . That's $t_{p H L}$ .
Go from 90 % down to 10 %: $t = τ ln \frac{0.9}{0.1} = τ ln 9 \approx 2.2 τ$ . That's $t_{f}$ .

Why 10–90 % and not 0–100 %: the curve never actually reaches $0$ (or the rail on the way up) — it only sneaks closer forever. Asking "time to hit exactly 0" gives $ln (\infty) = \infty$ . So we clip the endless tails at 10 % and 90 %. That single fact is the reason the whole convention exists.

5. Width $W$ , length $L$ , and the ratio $W / L$

There's one catch the parent's mistakes-section warns about: making $W$ bigger also makes the transistor's own input a bigger bucket for whatever drives it. Balancing your own strength against the load you impose on others is the whole game of Logical Effort and Fan-out-of-4.

Also needed: electrons (in NMOS) move about twice as easily as holes (in PMOS) — a property called ==mobility $μ$ ==, with $μ_{n} \approx 2 μ_{p}$ . That's why a PMOS must be made ~2× wider to match an NMOS's strength — the source of the parent's "matched inverter" sizing.

6. How it all feeds the topic

Every arrow is a symbol you now own feeding into the final timing quantities. When the parent writes $t_{p H L} = 0.69 R_{e q} C_{L}$ , you can trace every letter back to a bucket, a hose, and a "how long?" button.

Equipment checklist

Cover the right side and answer aloud; reveal to check.

What does

i = \frac{d Q}{d t}

say in plain words?

Current is the rate at which charge flows — charge per second.

What does the master equation

i = C \frac{d V}{d t}

mean physically?

The current into a capacitor equals its size times how fast its voltage is rising.

What is

C_{L}

The total load capacitance — the combined "bucket" (wire + downstream gate inputs) on a gate's output node.

Why is the switching threshold at

V_{D D} /2

It's the halfway height where a downstream gate decides the logic value flipped.

What is the time constant

τ

and its formula?

The circuit's natural timescale;

τ = R_{e q} C_{L}

seconds — bigger cap or resistance ⇒ slower.

What does

ln

do and why do we need it here?

It undoes the exponential, letting us solve

e^{- t / τ} = f

for the time

t

Where does the

0.69

t_{p H L}

come from?

From

ln 2

, because we cross the 50 % point:

e^{- t / τ} = \frac{1}{2}

Where does the

2.2

t_{f}

come from?

From

ln 9

, the 90 %→10 % span.

Why not measure rise time from 0 % to 100 %?

The exponential approaches the rail asymptotically and never reaches it, so 0–100 % time is infinite.

How does

R_{e q}

scale with transistor width

W

R_{e q} \propto 1/ W

— wider transistor, lower resistance, faster edge.

Why must PMOS be ~2× wider than NMOS to match?

Hole mobility is ~half electron mobility (

μ_{n} \approx 2 μ_{p}

), so PMOS needs double width to reach the same drive.

Connections

Parent: 3.2.07 Propagation delay and rise - fall times (Hinglish)
CMOS Inverter DC Transfer Characteristic
Equivalent Resistance of MOSFET
Load Capacitance Estimation
Logical Effort and Fan-out-of-4
Dynamic Power Dissipation
Elmore Delay