Propagation delay and rise - fall times: Visual walkthrough

This page zooms into Model A (the RC picture) from the parent note and rebuilds it from nothing.

Step 1 — The one node that matters, and the bucket living on it

WHAT. An inverter is two switches stacked between the supply and ground. The only thing we care about for timing is a single wire: the output node. Hanging off that wire is a lump of stored charge we call the load capacitance $C_{L}$ .

WHY. All delay comes from moving charge onto or off of this one node. Everything else (the input pin, the other gate) is just what sets $C_{L}$ or what turns the switch on. So we throw the rest away and stare at this node.

PICTURE. Below, the output node is the dot. $V_{D D}$ (the pale-yellow rail at the top) is the supply voltage — the "high" level. Ground is the bottom rail (0 volts). The blue box is the pull-down switch (the NMOS transistor). The load $C_{L}$ is drawn as a bucket that stores charge.

Figure — Propagation delay and rise - fall times

Step 2 — Close the switch: charge starts leaving the bucket

WHAT. The input jumps high, which closes the pull-down switch (turns the NMOS on). Now there is a path from the charged output node down to ground. Charge drains out.

WHY. Before this instant the bucket sat full at $V_{o u t} = V_{D D}$ . Nothing was moving. The switch closing is the event that starts the clock — this is the "input crosses 50%" moment.

PICTURE. The blue switch is now a closed wire. A pink current arrow $i_{D N}$ carries charge off the node, down through the transistor, to ground. As charge leaves, $V_{o u t}$ (yellow) starts sagging from the top rail.

Step 3 — The rule of the bucket (charge conservation)

WHAT. We write down the one physical law of a capacitor: the current into it equals capacitance times how fast its voltage changes.

$bucket size C_{L} how fast level moves \frac{d V _{o u t}}{d t} = - drain current out i_{D N} (t)$

WHY. This is nothing but $Q = C_{L} V_{o u t}$ differentiated in time: $\frac{d Q}{d t} = C_{L} \frac{d V _{o u t}}{d t}$ , and $\frac{d Q}{d t}$ is the current. The minus sign is the whole story of falling: current leaving ( $i_{D N} > 0$ ) makes $\frac{d V _{o u t}}{d t} < 0$ , so the level drops.

Term by term:

$C_{L} \frac{d V _{o u t}}{d t}$ — the rate charge is stored on the node.
$- i_{D N}$ — the rate charge is removed. Stored = −removed, so they balance.

PICTURE. A tilted bucket: the higher the drain current arrow, the steeper the downward slope of the water line. Same bucket, two drain strengths, two slopes.

Step 4 — The resistor guess, and why it's an exponential

WHAT. When the voltage across the transistor is small, an on-transistor behaves like a plain resistor $R_{e q}$ . A resistor obeys Ohm's law: $i_{D N} = V_{o u t} / R_{e q}$ . Put that into the bucket rule:

$C_{L} \frac{d V _{o u t}}{d t} = - \frac{V _{o u t}}{R _{e q}}$

WHY this tool — why a resistor? Because a resistor is the simplest device whose current is proportional to voltage, and that proportionality is exactly what produces an exponential decay. We reach for the exponential because it is the one function whose rate of change is proportional to itself — and the equation above literally says "rate of $V_{o u t}$ ∝ $V_{o u t}$ ." No other elementary function does that. See Equivalent Resistance of MOSFET for where $R_{e q}$ actually comes from.

The solution (the function that satisfies it) is:

$V_{o u t} (t) = V_{D D} e^{- t / τ}, τ = R_{e q} C_{L}$

Term by term:

$V_{D D}$ — the starting height (at $t = 0$ , $e^{0} = 1$ , so $V_{o u t} = V_{D D}$ ). ✔
$e^{- t / τ}$ — the fraction remaining; it shrinks toward 0 but never reaches it.
$τ = R_{e q} C_{L}$ — the time constant: bigger bucket or weaker (larger $R$ ) transistor ⇒ slower fall.

PICTURE. The falling yellow curve. At $t = τ$ it has dropped to $37%$ ( $e^{- 1}$ ) of $V_{D D}$ ; the dashed asymptote is the ground rail it approaches forever.

Step 5 — Reading the delay off the curve: where does $0.69$ come from?

WHAT. Propagation delay $t_{p H L}$ is the time for the output to reach the halfway line $V_{D D} /2$ — the logic decision level. So we ask the curve: when are you at half height?

$\frac{V _{D D}}{2} = V_{D D} e^{- t_{p H L} / τ} ⟹ e^{- t_{p H L} / τ} = \frac{1}{2}$

WHY halfway? Because $V_{D D} /2$ is the threshold where the next gate down the line changes its mind about whether the input is a 1 or a 0. That is when the signal has effectively "arrived."

WHY the logarithm — why $ln$ ? We have the unknown time $t_{p H L}$ trapped inside an exponent. The natural logarithm is precisely the tool that undoes $e^{(\cdot)}$ — it answers "to what power must I raise $e$ to get this number?" Taking $ln$ of both sides frees $t_{p H L}$ :

$- \frac{t _{p H L}}{τ} = ln \frac{1}{2} = - ln 2 ⟹ t_{p H L} = τ ln 2 = 0.69 R_{e q} C_{L}$

PICTURE. The curve crosses the pink $V_{D D} /2$ line; drop a vertical to the time axis and that intercept is $t_{p H L} = 0.69 τ$ . The label $ln 2$ sits right on the crossing.

Step 6 — The same curve gives fall time: where does $2.2$ come from?

WHAT. Fall time $t_{f}$ is the time to slide from $90%$ down to $10%$ of $V_{D D}$ — the steepness of the edge, on the output alone. We ask the curve for two times and subtract.

Time to reach a level $x V_{D D}$ : from $x = e^{- t / τ}$ we get $t = τ ln (1/ x)$ . So

$t_{f} = time to reach 10% τ ln \frac{1}{0.1} - time to reach 90% τ ln \frac{1}{0.9} = τ ln \frac{0.9}{0.1} = τ ln 9 = 2.2 R_{e q} C_{L}$

WHY subtract? Delay $t_{p H L}$ was measured from a fixed start ( $t = 0$ ). Fall time is measured between two points on the same edge, so we take the later time minus the earlier time — the difference erases the start.

WHY $10$ – $90%$ and not $0$ – $100%$ ? The exponential never truly reaches $0$ (the asymptote in Step 4). The $0%$ time is infinite. Clipping to $10$ – $90%$ makes it finite and repeatable.

PICTURE. Two horizontal lines at $0.9 V_{D D}$ and $0.1 V_{D D}$ ; the curve pierces them at two times; the shaded gap between those times is $t_{f} = 2.2 τ$ .

Step 7 — The degenerate case: strong drain, big swing (constant-current model)

WHAT. Early in the fall $V_{o u t}$ is near $V_{D D}$ , so the voltage across the transistor is large — it is saturated and delivers a roughly constant current $I_{D S A T}$ , not $V / R$ . Then the bucket rule becomes:

$C_{L} \frac{d V _{o u t}}{d t} = - I_{D S A T} = constant ⟹ V_{o u t} (t) = V_{D D} - \frac{I _{D S A T}}{C _{L}} t$

WHY a straight line? A constant current means a constant slope — the level falls like a ramp, not a curve. This is the opposite extreme from Step 4's resistor.

Setting $V_{o u t} = V_{D D} /2$ (still the halfway rule):

$t_{p H L} = \frac{C _{L} ( V _{D D} /2 )}{I _{D S A T}} = \frac{C _{L} V _{D D}}{2 I _{D S A T}}$

Term by term: numerator $C_{L} (V_{D D} /2)$ = the charge we must remove to drop half the swing; denominator $I_{D S A T}$ = how fast we remove it. Charge ÷ rate = time.

PICTURE. Two curves overlaid on the same axes: the resistor's bending exponential (Step 4) and the constant-current straight ramp — both hit $V_{D D} /2$ , both give a $t_{p H L} \propto C_{L} / drive$ .

The one-picture summary

Everything above compressed onto one board: the input step launches the fall at $t = 0$ ; the output slides down along the exponential; the $50%$ crossing marks $t_{p H L} = 0.69 τ$ ; the $10%$ – $90%$ band marks $t_{f} = 2.2 τ$ ; and the whole shape is set by $τ = R_{e q} C_{L}$ .

Recall Feynman retelling — the whole walkthrough in plain words

There is one wire whose voltage we watch. Sitting on it is a bucket of charge, size $C_{L}$ . When the input flips, a switch (the NMOS) opens a drain to ground and charge pours out. The pour rate is set by how the transistor pushes current: if we picture it as a resistor, the level falls in a bending curve $V_{D D} e^{- t / τ}$ with $τ = R_{e q} C_{L}$ ; if we picture it as a fixed hose, the level falls in a straight ramp. Either way, the delay is the moment the level passes the halfway mark — for the curve that is $ln 2 = 0.69$ time constants, because you undo the exponent with a logarithm. The fall time is how long the level takes to slide from nearly-full ( $90%$ ) to nearly-empty ( $10%$ ) — that is $ln 9 = 2.2$ time constants, always $3.17$ times the delay. We never wait for exactly empty, because an exponential trickles toward the floor forever. Bigger bucket or weaker transistor ⇒ everything is slower. That single sentence — $t_{p} \propto C_{L} / drive$ — is the whole chapter.

Recall

The $0.69$ in $t_{p H L}$ comes from where? ::: $ln 2$ , from setting $e^{- t / τ} = \frac{1}{2}$ at the $50%$ crossing. Why does a logarithm appear at all? ::: The unknown time sits inside an exponent; $ln$ is the tool that undoes $e^{(\cdot)}$ and frees it. Why is $0$ – $100%$ never used for fall time? ::: The exponential approaches ground asymptotically, so $0%$ is reached only at infinite time. One sentence for the whole page? ::: Delay is charge over drive: $t_{p} \propto C_{L} / (drive strength)$ .

Connections

Parent: 3.2.07 Propagation delay and rise - fall times (Hinglish)
Equivalent Resistance of MOSFET — where $R_{e q}$ comes from.
Load Capacitance Estimation — where $C_{L}$ comes from.
Logical Effort and Fan-out-of-4 — tuning drive strength.
Elmore Delay — chaining many RC stages.
CMOS Inverter DC Transfer Characteristic — the static picture behind the switch.
Dynamic Power Dissipation — the energy cost of the same charging.