Propagation delay and rise - fall times: Worked examples

Before line one, three tiny reminders so no symbol is unearned:

Definition Symbol legend (all reused below)

$C_{L}$ = load capacitance: the total charge-holding ability of the output node (wire + downstream gate inputs), measured in farads (F). Picture a bucket; bigger bucket = more charge to move.
$R_{e q}$ = equivalent resistance of the conducting transistor: how much it "resists" the flow of charge, measured in ohms (Ω). Picture a narrow pipe; narrower = more resistance = slower. See Equivalent Resistance of MOSFET.
$τ = R_{e q} C_{L}$ = the time constant: the natural timescale of one bucket-through-one-pipe. Everything is measured in multiples of $τ$ .
$I_{D S A T}$ = saturation current: the roughly constant current a strongly-driven transistor pushes, in amps (A). Picture the maximum flow rate of the hose.
$V_{D D}$ = supply voltage (the "full" bucket level); $V_{50%} = V_{D D} /2$ is the logic decision level.
$t_{p H L}$ = propagation delay, High→Low: the lag from the input crossing 50% to the output crossing 50% while the output falls. Measured in seconds (s). Picture "time until the bucket is half-empty."
$t_{p L H}$ = propagation delay, Low→High: the same lag while the output rises (PMOS charging the bucket up to half-full).
$t_{f}$ = fall time: how long the output alone takes to slide from $90%$ down to $10%$ of $V_{D D}$ — the steepness of a falling edge, in seconds.
$t_{r}$ = rise time: the same $10% \to 90%$ span for a rising edge.
$t_{p} = \frac{1}{2} (t_{p H L} + t_{p L H})$ = the overall gate delay, one representative number averaging both edges.

Unit shorthand used everywhere: $f = 1 0^{- 15}$ (femto), $p = 1 0^{- 12}$ (pico), $μ = 1 0^{- 6}$ (micro), $k = 1 0^{3}$ (kilo).

The scenario matrix

Every problem this topic can throw is one of these cells. The right column names the example that covers it.

#	Case class	What makes it tricky	Covered by
A	Plain RC delay (well-behaved)	just plug in $0.69 τ$	Ex 1
B	Rise/fall vs delay (two conventions on one edge)	50% vs 10–90% mix-up	Ex 2
C	Constant-current model	half-swing charge only	Ex 3
D	Asymmetric H→L vs L→H (both signs of the edge)	$R_{e q n} \neq = R_{e q p}$	Ex 4
E	Sizing to match (solve for $W$ )	inverse: given target, find geometry	Ex 5
F	Degenerate: $I_{D S A T} \to 0$ (weak / cut-off transistor)	delay $\to \infty$ ; limiting behaviour	Ex 6
G	Degenerate: $C_{L} \to 0$ (unloaded gate)	delay $\to 0$ ; what actually limits it	Ex 6
H	Real-world word problem (max clock frequency)	translate delay → MHz	Ex 7
I	Exam twist: model disagreement	RC vs constant-I give different numbers — which and why	Ex 8

Example 1 — Cell A: plain RC delay

Forecast: guess first — is $t_{p H L}$ bigger or smaller than $τ$ ? (It must be smaller: we only wait until half-way, not one full time constant.)

Compute $τ = R_{e q} C_{L}$ . $τ = 8 \times 1 0^{3} \times 25 \times 1 0^{- 15} = 2.0 \times 1 0^{- 10} s = 200 ps$ Why this step? $τ$ is the single knob that sets the whole timescale; every delay is a pure number times $τ$ .
Multiply by $ln 2 \approx 0.69$ . $t_{p H L} = 0.69 τ = 0.69 \times 200 = 138 ps$ Why $0.69$ ? The output falls as $V (t) = V_{D D} e^{- t / τ}$ ; setting $V = V_{D D} /2$ gives $e^{- t / τ} = \frac{1}{2}$ , so $t = τ ln 2$ .

Figure — Propagation delay and rise - fall times

How to read the figure: the cyan curve is the output voltage falling exponentially from the full rail ( $V_{D D}$ , the top) toward ground. The horizontal amber dashed line marks the $50%$ level $V_{D D} /2$ ; the amber dot is exactly where the curve crosses it. Drop straight down from that dot to the time axis and you read off $t_{p H L} = 0.69 τ$ — notice it lands before the $t = τ$ tick, which is our whole forecast made visible. The two white dotted lines at $90%$ and $10%$ are there for the next example.

Verify: $138 ps < 200 ps = τ$ ✓ (matches the forecast — half-way happens before one full $τ$ ). Units: $Ω \cdot F = \frac{V}{A} \cdot \frac{A \cdot s}{V} = s$ ✓.

Example 2 — Cell B: rise/fall vs delay on the same edge

Forecast: which is longer, $t_{f}$ or $t_{p H L}$ ? The fall time watches a longer stretch of the curve (10% to 90%), so predict $t_{f} > t_{p H L}$ .

Fall time uses $ln 9$ , not $ln 2$ . $t_{f} = τ ln 9 = 2.2 τ = 2.2 \times 200 = 440 ps$ Why $ln 9$ ? Going from $0.9 V_{D D}$ down to $0.1 V_{D D}$ : the time is $τ [ln \frac{V _{D D}}{0.1 V _{D D}} - ln \frac{V _{D D}}{0.9 V _{D D}}] = τ ln \frac{0.9}{0.1} = τ ln 9$ .
Take the ratio. $\frac{t _{f}}{t _{p H L}} = \frac{τ l n 9}{τ l n 2} = \frac{l n 9}{l n 2} \approx 3.17$ Why does $τ$ cancel? Both are the same exponential; the ratio depends only on the voltage levels, never on $R$ or $C$ . This is a universal fingerprint of RC discharge.

How to read the figure (reuse Fig 1): look again at the two white dotted lines at $90%$ and $10%$ . The fall time is the horizontal distance the cyan curve travels between those two lines — a much wider slice of time than the single amber $50%$ crossing used in Ex 1. Seeing that the $10 \to 90%$ span is visibly wider than the $100 \to 50%$ span is why $t_{f} > t_{p H L}$ .

Verify: $440/138 = 3.19 \approx 3.17$ ✓ (tiny gap is rounding of $0.69$ and $2.2$ ). Forecast confirmed: $t_{f} > t_{p H L}$ .

Example 3 — Cell C: constant-current model

Forecast: the model says $V (t)$ falls as a straight line (constant current ⇒ constant slope), not a curve. So we only need the charge to drop the half swing $V_{D D} /2$ .

Charge to remove for a half swing. $Q = C_{L} \cdot \frac{V _{D D}}{2} = 12 \times 1 0^{- 15} \times 0.5 = 6.0 \times 1 0^{- 15} C$ Why half? Delay is measured to $V_{D D} /2$ ; only that much charge must leave before the next gate flips.
Time = charge / current. $t_{p H L} = \frac{Q}{I _{D S A T}} = \frac{6.0 \times 1 0 ^{- 15}}{150 \times 1 0 ^{- 6}} = 4.0 \times 1 0^{- 11} s = 40 ps$ Why divide? $i = d Q / d t$ with constant $i$ gives $t = Q / i$ — the hose empties the bucket at a fixed rate.

How to read the figure: the amber straight line is the constant-current model — a fixed slope, because a fixed current removes charge at a fixed rate. The cyan dashed curve is the RC exponential for comparison; both are tuned to cross the white dotted $V_{D D} /2$ line at the same instant (the white dot). The amber arrow highlights that only the upper half of the swing (down to $V_{D D} /2$ ) counts toward $t_{p H L}$ — everything below the decision level is irrelevant to the delay number.

Verify: compact form $t_{p H L} = \frac{C _{L} V _{D D}}{2 I _{D S A T}} = \frac{12 f \times 1.0}{2 \times 150 μ} = \frac{1.2 \times 1 0 ^{- 14}}{3.0 \times 1 0 ^{- 4}} = 40 ps$ ✓. Units: $\frac{F \cdot V}{A} = \frac{C}{A} = s$ ✓.

Example 4 — Cell D: asymmetric H→L and L→H

Forecast: the PMOS is weaker (bigger $R$ ), so the rising edge ( $t_{p L H}$ ) should be slower. The overall delay is an average, so it lands between the two.

Falling edge (NMOS pulls down). $t_{p H L} = 0.69 R_{e q n} C_{L} = 0.69 \times 6 k \times 20 f = 0.69 \times 1.2 \times 1 0^{- 10} = 82.8 ps$ Why $R_{e q n}$ ? Output going High→Low is the NMOS discharging $C_{L}$ .
Rising edge (PMOS pulls up). $t_{p L H} = 0.69 R_{e q p} C_{L} = 0.69 \times 15 k \times 20 f = 0.69 \times 3.0 \times 1 0^{- 10} = 207 ps$ Why $R_{e q p}$ ? Output going Low→High is the PMOS charging $C_{L}$ from the supply.
Overall gate delay = average of the two edges. $t_{p} = \frac{1}{2} (t_{p H L} + t_{p L H}) = \frac{1}{2} (82.8 + 207) = 144.9 ps$ Why average? A real signal path sees both transitions in roughly equal proportion, so the representative delay is their mean.

Verify: ratio $t_{p L H} / t_{p H L} = 207/82.8 = 2.5 = R_{e q p} / R_{e q n} = 15/6$ ✓ (delay tracks resistance exactly). Forecast confirmed: rising edge slower, $t_{p}$ sits between them.

Example 5 — Cell E: inverse problem, size to match

Forecast: because $R_{e q} \propto 1/ W$ , to lower the PMOS resistance to match, we must widen it. Predict $W_{p} = 2 W_{n}$ .

Baseline PMOS resistance at $W_{p} = 1$ . At equal width, $R_{e q p} (W_{p} = 1) = 2 R_{e q n} = 2 \times 5 k = 10 k Ω$ . Why 2×? Half the mobility ⇒ half the current at the same $W$ ⇒ double the resistance.
Scale width to hit $R_{e q p} = R_{e q n}$ . Since $R_{e q p} \propto 1/ W_{p}$ , we need $W_{p}$ such that $\frac{10 k}{W _{p}} = 5 k$ , giving $W_{p} = \frac{10 k}{5 k} = 2 \Rightarrow W_{p} = 2 W_{n}$ Why this scaling? Doubling width doubles the current-carrying channel, halving resistance — exactly the factor 2 we need to cancel the mobility handicap.
Matched delay per edge. Now $R_{e q p} = R_{e q n} = 5 k Ω$ , so $t_{r} = t_{f} = 2.2 R_{e q} C_{L} = 2.2 \times 5 k \times 10 f = 110 ps$ and $t_{p L H} = t_{p H L} = 0.69 \times 5 k \times 10 f = 34.5 ps$ . Why the factor $2.2$ here? $t_{r}$ and $t_{f}$ are $10% \to 90%$ edge times, and (as derived in Ex 2) that span of a pure exponential is $τ ln 9 = 2.2 τ$ — the same $ln 9$ logic, now applied to the matched resistance. The $0.69$ line uses $ln 2$ because those are $50%$ delays.

Verify: with $R_{e q p} = R_{e q n}$ , edges are equal ⇒ $t_{r} = t_{f}$ ✓, forecast $W_{p} = 2 W_{n}$ ✓. See Logical Effort and Fan-out-of-4 for why this "matched" inverter is the reference for effort calculations.

Example 6 — Cells F & G: the two degenerate limits

Forecast: a dying hose can never empty the bucket (delay blows up); an empty bucket needs no emptying (delay vanishes). Predict $\infty$ and $0$ respectively.

Cell F — $I_{D S A T} \to 0$ (transistor cut off / very weak). $t_{p H L} = \frac{C _{L} V _{D D}}{2 I _{D S A T}} I_{D S A T} \to 0 + \infty$ Why? Zero drive current means no charge ever leaves $C_{L}$ ; the output never reaches $V_{D D} /2$ , so the delay is unbounded. Equivalently in the RC view $R_{e q} \to \infty$ and $τ \to \infty$ . A gate whose input never turns it on has no defined delay — it simply does not switch.
Cell G — $C_{L} \to 0$ (unloaded output). $t_{p H L} = 0.69 R_{e q} C_{L} C_{L} \to 0 0$ Why? No bucket to empty ⇒ nothing to wait for. But physically it is never exactly zero: there is always the transistor's own drain/junction capacitance (its "self-load"). So the true floor is $t_{p H L} = 0.69 R_{e q} C_{self} > 0$ , the intrinsic delay.

Verify (Cell F — carried through with numbers): to show the limit diverges, freeze the numerator by setting $C_{L} V_{D D} = 1$ (whatever units), so $t_{p H L} = \frac{1}{2 I _{D S A T}}$ , and shrink $I_{D S A T}$ by factors of ten:

$I_{D S A T} = 100 μ A \Rightarrow t_{p H L} = \frac{1}{2 \times 100 \times 1 0 ^{- 6}} = 5.0 \times 1 0^{3}$

$I_{D S A T} = 10 μ A \Rightarrow t_{p H L} = \frac{1}{2 \times 10 \times 1 0 ^{- 6}} = 5.0 \times 1 0^{4}$

$I_{D S A T} = 1 μ A \Rightarrow t_{p H L} = \frac{1}{2 \times 1 \times 1 0 ^{- 6}} = 5.0 \times 1 0^{5}$

Each tenfold drop in current multiplies the delay by exactly ten — the sequence $5 \times 1 0^{3}, 5 \times 1 0^{4}, 5 \times 1 0^{5}, \dots$ grows without bound, so $t_{p H L} \to + \infty$ as $I_{D S A T} \to 0$ ✓. Verify (Cell G): $0.69 \times R_{e q} \times 0 = 0$ ✓. Together these two cells bracket every real answer strictly between $0$ and $\infty$ .

Example 7 — Cell H: real-world max-frequency word problem

Forecast: more stages = more total delay = lower max frequency. Five stages of 30 ps is 150 ps total, and frequency is one-over-time, so expect a few gigahertz.

Total path delay = sum of stage delays. $t_{path} = 5 \times t_{p} = 5 \times 30 ps = 150 ps$ Why sum? Signals traverse stages one after another; the lags add linearly along the path.
Max frequency = 1 / (path delay). $f_{m a x} = \frac{1}{t _{path}} = \frac{1}{150 \times 1 0 ^{- 12}} = 6.67 \times 1 0^{9} Hz = 6.67 GHz$ Why the reciprocal? One clock period must be at least as long as the slowest path so the signal settles before it is sampled; the fastest allowed period is exactly $t_{path}$ , and $f = 1/ T$ .

Verify: $6.67 GHz \times 150 ps = 6.67 \times 1 0^{9} \times 150 \times 1 0^{- 12} = 1.0$ ✓ (period times frequency = 1). Sanity: matches the forecast of "a few GHz." (Real chips add setup/hold margins and wire delay, lowering $f_{m a x}$ further — see Elmore Delay for distributed-wire timing.)

Example 8 — Cell I: exam twist, the two models disagree

Forecast: the RC model (small- $V_{D S}$ , resistive) and the constant-current model (large- $V_{D S}$ , saturated) describe different phases of the same switch, so their numbers need not match; expect them to be in the same ballpark but not identical.

RC model. $t_{p H L}^{R C} = 0.69 \times 10 k \times 10 f = 0.69 \times 1 0^{- 10} = 69 ps$
Constant-current model. $t_{p H L}^{C C} = \frac{C _{L} V _{D D}}{2 I _{D S A T}} = \frac{10 f \times 1.2}{2 \times 60 μ} = \frac{1.2 \times 1 0 ^{- 14}}{1.2 \times 1 0 ^{- 4}} = 100 ps$
Reconcile — which to trust, and why. Why the gap? At the start of the fall the output is near $V_{D D}$ , so $V_{D S}$ is large and the transistor sits in saturation — a nearly constant current — which is exactly the constant-current model's home turf. As the output approaches ground, $V_{D S}$ shrinks and the transistor slides into the resistive (triode) region, which is the RC model's home turf. The takeaway: neither number is "the right answer" — each is exact only in its own regime, and the true delay is a blend. Because $t_{p H L}$ is measured only down to $V_{D D} /2$ (still fairly high $V_{D S}$ ), the transition spends most of the measured interval in saturation, so the constant-current estimate (100 ps) is usually the more trustworthy of the two, and a full SPICE simulation lands between $69$ and $100$ ps. Rule of thumb for exams: when both are offered and no regime is specified, quote the constant-current value for the delay-to-50% and note the RC value as the fast-limit.

Verify: both share the proportionality $t_{p} \propto C_{L}$ : double $C_{L}$ and both double. Ratio $t^{C C} / t^{R C} = 100/69 = 1.45$ — a fixed factor set only by whether $R_{e q}$ was pinned to the end-of-transition current or the saturation current (CMOS Inverter DC Transfer Characteristic shows where each regime lives on the curve). ✓ Forecast confirmed: same ballpark, not identical.

Recall Self-test across the whole matrix

Which cell needs $ln 9$ not $ln 2$ ? ::: Cell B — rise/fall time (10–90%); delay (50%) uses $ln 2$ . As $I_{D S A T} \to 0$ , what is $t_{p H L}$ ? ::: $+ \infty$ — a non-switching gate has no finite delay (Cell F). Two models give 69 ps and 100 ps — which to trust and why? ::: The constant-current 100 ps, because the transition to 50% stays mostly in saturation; SPICE lands between (Cell I). Path of 5 stages at 30 ps → max clock? ::: $1/ (5 \times 30 ps) = 6.67 GHz$ (Cell H). To match $t_{r} = t_{f}$ with $μ_{n} = 2 μ_{p}$ , set $W_{p} = ?$ ::: $W_{p} = 2 W_{n}$ , halving $R_{e q p}$ to equal $R_{e q n}$ (Cell E).

Connections

Parent: Propagation delay and rise - fall times
3.2.07 Propagation delay and rise - fall times (Hinglish)
Equivalent Resistance of MOSFET — where $R_{e q}$ (Ex 1, 4, 8) comes from.
Load Capacitance Estimation — the intrinsic- $C$ floor of Cell G.
Logical Effort and Fan-out-of-4 — the sizing logic behind Ex 5.
Dynamic Power Dissipation — the energy cost of the same charging.
CMOS Inverter DC Transfer Characteristic — which regime (Ex 8) lives where.
Elmore Delay — extends Cell H to distributed wires.