Step 1 — model the switching.
When the output drives h identical gate loads, the total load capacitance is:
CL=hCg+CparWhy this step? Each downstream input is essentially a capacitor Cg; h of them add in parallel, plus the driver's own self/parasitic capacitance Cpar.
Step 2 — write the delay as RC.
The transistor charging this cap has on-resistance R. The propagation delay is proportional to the RC product:
tpd=0.69RCLWhy this step? Solving V(t)=VDD(1−e−t/RC) for the 50% point gives t=RCln2=0.69RC. That's where "0.69" comes from — it is derived, not magic.
Step 3 — normalize (logical effort form).
Define the electrical effort (a.k.a. fan-out) as:
f=CinCL
Then delay (in normalized units) is:
d=g⋅f+p
where g = logical effort (how much worse the gate is than an inverter), f = electrical effort (fan-out), p = parasitic delay.
Step 1 — series resistance adds.
Put N NMOS transistors in series (a NAND-N). Resistances in series add:
Rstack=NRWhy this step? Ohmic series resistances sum. The pull-down path is now N times more resistive.
Step 2 — sizing to compensate.
To keep resistance constant you widen each transistor by N → but wider transistors have N× bigger input capacitance. So each input load grows, raising the previous stage's fan-out.
Step 3 — parasitic capacitance grows.
The internal source/drain junctions between stacked transistors each add capacitance. Parasitic delay scales roughly:
pNAND-N≈Npinv
Why NOR is worse: the "2N" comes from stacking PMOS (mobility ~2× worse), so wider PMOS = more capacitance per unit drive.
The number of inputs = number of transistors in series in the pull-up or pull-down network.
What is fan-out?
The number of gate-input loads a single output must drive (total load capacitance / one input cap).
Why does fan-out increase delay?
Each load adds capacitance Cg; delay =0.69RCL grows linearly with load, so d=gf+p with f=Cout/Cin.
Where does the 0.69 in RC delay come from?
Solving the 50% point of V=VDD(1−e−t/RC) gives t=RCln2=0.69RC.
Logical effort of a NAND-N gate?
g=(N+2)/3.
Logical effort of a NOR-N gate?
g=(2N+1)/3.
Why is NOR worse than NAND for high fan-in?
NOR stacks weak PMOS in series; PMOS mobility ~2× lower so its logical effort grows ~2× faster.
How does parasitic delay scale with fan-in N?
Roughly p≈Npinv due to added internal junction caps.
Fix for a high-fan-in gate?
Split into a balanced tree of low-fan-in gates.
Fix for a high-fan-out net?
Insert buffers / upsize the driver (or a buffer tree), trading area/prior-stage load for speed.
Delay equation in logical-effort form?
d=gf+p, where g=logical effort, f=electrical effort (fan-out), p=parasitic delay.
In pure CMOS, what limits fan-out — current or capacitance?
Capacitance (speed); gate leakage is ~0 so DC current limit is negligible.
Recall Feynman: explain to a 12-year-old
Imagine one kid (the gate) pouring water into cups (the loads). If he pours into 2 cups it's quick; into 10 cups it takes ages — that's fan-out. Now imagine a line of kids passing a bucket one after another before the water reaches the end — a long line is slow, that's fan-in (many transistors in a row). To go fast: don't make one kid fill 20 cups, and don't make a line of 8 kids. Use short lines and many helpers (small gates, buffers).
Dekho, ek CMOS gate koi superhero nahi hai — uski taakat limited hoti hai. Fan-in ka matlab hai gate ke kitne inputs hain, yaani pull-down ya pull-up network mein kitne transistors series mein lage hain. Jitne zyada series transistors, utni zyada resistance (Rstack=NR), aur beech ke junctions ki wajah se parasitic capacitance bhi badhti hai — toh gate slow ho jaata hai. Isliye ek hi 8-input NAND banane se accha hai chhote 2-input gates ka balanced tree banao.
Fan-out ka matlab hai ek output kitne dusre inputs ko drive kar raha hai. Har input ek chhota capacitor (Cg) jaisa hai, aur output ko yeh saari capacitance charge/discharge karni padti hai. Delay basically 0.69RCL hoti hai — yeh 0.69 aayi kahan se? V=VDD(1−e−t/RC) ko 50% pe solve karo toh t=RCln2=0.69RC nikalta hai. Normalized form mein delay d=gf+p, jahan f hi fan-out hai. Zyada loads = zyada f = zyada delay, seedha linear.
Yaad rakhne ka trick: "IN series, OUT parallel" — fan-in transistors series mein (resistance add), fan-out loads parallel mein (capacitance add). Dono delay badhaate hain. Aur ek important baat: NOR is poorer — kyunki NOR mein PMOS series mein aata hai jo weak hota hai, isliye CMOS mein hamesha NAND logic prefer karo. High fan-out theek karne ke liye buffer laga do ya driver ko bada kar do (par dhyaan rakho, driver bada karoge toh uska input cap badhega aur pichhli stage pe load aayega — effect peeche tak jaata hai).
